Hm, my email did not go through and Matthew's got only to my gmail address. To Matthew: we will go to the third route e.g. generating an internal calibration signal so the hardware can be calibrated when needed.
Here is my email again (slightly edited) via gmail: ------------------ Hi Vereese and Jack, Well, safely is quite a strong word 😂, you have to be careful with clock and signal phase difference between the ADC's. We (mainly @Bela) have been testing interleaving and also IQ sideband separation. Sideband separation would in fact be even easier to combine two ADC's if you are mixing RF to baseband anyway. We are currently working on a wideband backend and one board will take two 8 GHz (e.g. pol.) channels from 2 - 18 GHz IF. We will be using KnowledgeResources modules ( https://www.knowres.com/product/krm-4zu48dr/?portfolioCats=148) and custom carrier board for baseband conversion and clock generation. Everything will be public when the project is in usable state. Cheers, Kaj On Thu, 9 Jan 2025 at 14:56, Vereese Van Tonder <vere...@sarao.ac.za> wrote: > Great, thanks Jack. So one can safely interleave 2 ADCs (both located > within 1 tile) upto 8 GSPS for 4 separate inputs. > > Have a good one. > > > On Thu, Jan 9, 2025 at 2:49 PM Jack Hickish <jackhick...@gmail.com> wrote: > >> (Though see >> https://adaptivesupport.amd.com/s/question/0D52E00006hpOwBSAU/rfsoc-multitile-adc-interleaving?language=en_US >> if interleaving is your desire) >> >> >> >> On Thu, 9 Jan 2025, 12:43 Jack Hickish, <jackhick...@gmail.com> wrote: >> >>> Hi Vereese, >>> >>> Happy 2025! >>> >>> The quoted 4G is per ADC, not per tile, so the ZCU111 really does have >>> 8x4GSPS samplers. The total sampling rate is indeed 32 GSPS (but this >>> doesn't mean that you can trivially interleave all 8 channels to achieve a >>> single super-high sample rate) >>> >>> Cheers >>> Jack >>> >>> On Thu, 9 Jan 2025, 12:22 Vereese Van Tonder, <vere...@sarao.ac.za> >>> wrote: >>> >>>> Hi ZCU111 users, >>>> >>>> I'm looking at: >>>> >>>> https://docs.amd.com/r/en-US/ug1271-zcu111-eval-bd/SI5382A-SFP28-Clock-Recovery >>>> which states: >>>> "The ZU28DRF-FFVG1517 contains eight multi-gigasample (4 GSPS), 12-bit >>>> RF analog-to-digital converter (RF-ADC) channels across four banks" >>>> >>>> From this I understand that a ZCU111 board can provide upto 32 GSPS - >>>> is this correct? Or does a tile (which contains 2 ADCs) provide 4GSPS in >>>> total, i.e. each is clocking at only 2GSPS and therefore the board can >>>> provide 16 GSPS in total? >>>> >>>> Thanks in advance and happy 2025. >>>> >>>> >>>> *Disclaimer* >>>> >>>> The information contained in this communication from the sender is >>>> confidential. It is intended solely for use by the recipient and others >>>> authorized to receive it. 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