> On Jun 7, 2017, at 1:01 PM, Jon Elson via cctech <cct...@classiccmp.org>
> wrote:
>
> On 06/07/2017 09:12 AM, william degnan via cctech wrote:
>> Where there any computers that used a "rectangular sense" core RAM?
>> Whirlwind core is diagonal. This page describes the differences/evolution
>> of the sense line.
>>
>> More: http://ed-thelen.org/comp-hist/Byte/76jul.html
>>
>> Were rectangular core planes used in any commercial/government computer
>> that saw production activity, presumably the period 1953-1959? Whirlwind
>> is known for diagonal sense planes, but was there a brief period when the
>> core was "rectangular sense" I know core was added to Whirlwind as an
>> upgrade, it did not launch into production with core. (right?)
>>
>>
> I think IBM LCS on the mid-scale 360s were rectangular. I assume by
> rectangular you mean that all wires were on a rectangular grid, parallel to
> the select wires. The google article on core memory shows a CDC 6600 core
> plane that shows no sign of diagonal wires.
Are you talking about the Wikipedia article, the photo of the 6600 core memory?
That photo is severely misleading. The "inset" is something entirely
different.
6600 core memory is documented in great detail in the training manual which is
on Bitsavers. It has conventional diagonal sense lines. It does have some
interesting design attributes, though. For one thing, it has pairs of inhibit
wires each carrying half the inhibit current. Also, there are four X inhibit
and four Y inhibit lines, so you use four of the address bits to select which
inhibit "quadrant" is driven. The manual doesn't say why; I believe it is done
to limit the inductance and to keep the per-wire inductance roughly consistent
for the select (X and Y) and inhibit (X and Y) wires. The drive circuitry is
also interesting, featuring constant currents that are steered between an
idling inductor and the selected wire, rather than being switched on. All
these techniques seem to explain the very high performance -- full read/restore
cycle in about 800 ns, which in 1964 was way faster than what others were doing.
> I think many old core planes with big cores ran all wires on a square grid,
> as there was plenty of window area in the cores. When they went to smaller
> cores and combining the sense/inhibit winding, then the diagonal wire
> threaded more easily through the remaining window after the X and Y select
> wires were in place.
Normal layout is what the Wikipedia article shows: wires in X/Y direction for
the most part, cores at 45 degrees. The sense wires normally zigzag along the
diagonals.
One detail not often described (I found it called out in the EL-X8 training
manual) is that the sense wire routing is done so that it passes through cores
in alternating direction for any given row and column. The point of doing so
is that then the noise pulses from half-selected cores in the addressed row and
column very nearly cancel.
On the "inset" memory with just two wires: that's prpobably CDC 6000 series ECS
memory. That was slow (4.8 microsecond cycle) very large memory, 488 bit
words. The CDC manuals describe it as "word select". The text near that photo
describes the approach briefly (it would be nice to have more details). I
vaguely remember a photo showing a large rectangular core plane -- not clear
just how big, 256 by 488 would be a possibility, or 488 by 1024. If so, it
would be bits of the word arranged along one coordinate, word addresses along
the other.
paul
