> On Aug 30, 2017, at 9:52 AM, Noel Chiappa via cctalk <cctalk@classiccmp.org> > wrote: > >> From: Jerry Weiss > >> The processor will probably halt due to non-existent memory address. > > No, it'll take a NXM trap (through 4); what happens then depends on what the > trap handler is set to - if anything. > >> However, a P entered in ODT will attempt to continue the bootstrap. > > See above. I wouldn't bet on a 'P' doing anything useful. > >> If you have and cannot disable the LTC, it may work intermittently, >> depending on whether LTC interrupt occurs before he OS bootstrap loads. >> Its just a matter of timing. > > You could set the PS to 340 and the PC to the start of the bootstrap, and do > a 'P' to start it running. (Using 'G' to start the bootstrap will clear the > PS.) > > But I guess you've still got the NXM trap to contend with. If the bootstrap > doesn't set the trap handler up, you could manually key in the vector (at 4) > and a real simple trap handler (e.g. just dismiss, with an RTI), and you also > might have to set up the SP. >
I stand corrected on the NXM trap. However back in the day, we had a few LSI systems without an external LTC control that would not boot consistently. The “P” trick worked, perhaps owing to a double bus error…. (R6 not set up correctly). We never got into the details. As I mentioned in my own followup, the UC07 uses Power On Option to recover via the power trap. This sets the PSW without an instruction, avoiding any code that would have to select between a MTPS or MOV #340,@#PSW. The FRD bootstrap for the UC07 instructs the user to use ODT to set the PSW,but I don’t see how code @200 would work on an LSI 11/1 or 11/03 unless that 04 vector is set up and handles he recovery as Noel suggests.
