A brief description of "built-in" FPGA logic analysers seems worthwhile, a valuable if non-trivial option.
Most FPGA vendors provide IP to implement in vivo logic analysers organically in the FPGA fabric. Additionally, they provide a GUI to display / capture the data and to interactively configure qualifiers and triggering. The capabilities provided by AMD Xilinx, in Vivado, provide a good exemplar. https://docs.xilinx.com/r/en-US/ug936-vivado-tutorial-programming-debugging/Using-the-Vivado-Integrated-Logic-Analyzer https://www.xilinx.com/products/intellectual-property/ila.html https://www.xilinx.com/video/hardware/introduction-to-the-vivado-logic-analyzer.html Pods such as the Digilent digital discovery, based on a Spartan-6 FPGA, mentioned in my previous post typically use a USB host interface. The Vivado ILA typically uses the (JTAG) programming link. Consequently, the commercial LA pods and ILA technology are probably best viewed as cousins, interoperation may be possible but is not a given. The standard use case for an ILA is during FPGA code (VHDL or Verilog) development, where the focus is on the internal FPGA logic; e.g. providing an execution trace for a SIMD sequencer, for debug or verification. The use case Syste suggests is to connect a UUT to an FPGA (board) with the interest now in the external signals and logic; e.g. connecting an ADC EVB to an FPGA EVB to firstly inspect the interface signals and then exploit the data stream. Equally, as Syste suggests, a suitable FPGA EVB could simply be employed as a logic analyser. The capability of the ILA will of course be bounded by the available resources and one's deviousness: - JTAG interface : in general, neither slow not fast - fast memory for acquisition and buffering : on a low end FPGA / SOC - 1 to 2 Mbits of ~4 ns access time BRAM The "cost" of this "free" technology needs to be noted: - the FPGA EVB and JTAG interface will be relatively inexpensive - the FPGA vendors ILA IP and tools typically free - the XFU (exercise for User) elements are where the cost lies -- integrating UUT and FPGA EVB : modest effort / cost ? -- mastering Vivado, the ILA IP and block diagram configuration, VHDL/Verilog, timing constraints, ... In summary, a useful capability is available but without FPGA expertise exploitation would be difficult without a canned example Martin === From: Paul Koning via cctalk [mailto:cctalk@classiccmp.org] Sent: 14 March 2023 14:40 I noticed the sigrok.org devices list mentions one that is open source hardware, that sounds a bit like what Sytse was talking about. paul ==== From: Sytse van Slooten via cctalk [mailto:cctalk@classiccmp.org] Sent: 14 March 2023 12:33 Another option that I haven't seen mentioned: use the built-in logic analyzers that the fpga tool chains come with - you'd have to wire up an fpga and sample the signals you need, but all the complexity of triggering, buffering and displaying would be done by the tool chain. -- Sytse ==== From: Martin Bishop via cctalk [mailto:cctalk@classiccmp.org] Sent: 14 March 2023 07:51 https://digilent.com/shop/digital-discovery-portable-usb-logic-analyzer-and-digital-pattern-generator/ 32 ch at 200 MS/s and pleasantly inexpensive If I was buying, I would consider trying one
