On 2/27/24 14:09, Paul Koning via cctalk wrote: > Suppose you had schematics of, say, a KA-10. You could turn those gates into > VHDL or Verilog, and that should deliver an exact replica of the original > machine, bug for bug compatible. That assumes the timing quirks are > manageable, which for most machines should be true. (It isn't for a CDC > 6600.)
A section manager from years ago mentioned to me that, as a fresh EE out of school, his first job at CDC was measuring the loops of (taper pin) wire on the 6600 to which Seymour had attached tags that said "tune". --Chuck
