[cctalk] Re: Intel 8086 - 46 yrs. ago

[Paul Koning via cctalk]

> On Jun 13, 2024, at 2:00 PM, Chuck Guzis via cctalk <cctalk@classiccmp.org> 
> wrote:
> 
> On 6/13/24 10:32, Paul Koning via cctalk wrote:
>> Huh?  There is no direct connection between word length, register count, and 
>> pipeline length.  
> Indeed.  There are architectures with NO user-addressable registers.
> Some have memory-mapped registers, where a "register number" is merely
> shorthand for a memory address (i.e. implicit multiplier and base)
> 
> --Chuck

There are of course also machines that appear to have registers (in the sense 
that the instruction set refers to them) but the implementation is a chunk of 
memory.  The PDP-6 is one (and early PDP-10s without the "fast registers" 
option).  The Philips PR-8000 may be one as well; the ISA has 8 registers, 
times 8 because it has a separate set per interrupt priority level, but there 
is a variant of the store instruction that stores to any of these as if it were 
memory.  I'm not actually sure if it was implemented that way; 64 registers 24 
bits wide would be a substantial cost and bulk in a mid-1960s machine.

        paul