efriedma added inline comments.
================ Comment at: llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp:1927 + .add(predOps(ARMCC::AL)) + .addReg(ARM::LR); + ---------------- I think you need to ensure that lr actually contains the correct value, somehow. Normally the call will come before anything that would clobber lr, but you're not actually enforcing that anywhere: LR isn't listed as an input to BL_PUSHLR. To make this work correctly, I think the return address actually needs to be an argument to the BL_PUSHLR instruction. See ARMTargetLowering::LowerRETURNADDR for how to make an appropriate copy. ================ Comment at: llvm/test/CodeGen/ARM/gnu_mcount_nc.ll:6 +; RUN: llc -mtriple=thumbv7a-linux-gnueabihf -fast-isel %s -o - | FileCheck %s --check-prefix=CHECK-THUMB-FAST-ISEL +; RUN: llc -mtriple=thumbv7a-linux-gnueabihf -global-isel -global-isel-abort=2 %s -o - | FileCheck %s --check-prefix=CHECK-THUMB-GLOBAL-ISEL + ---------------- Please add -verify-machineinstrs to all these invocations. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D65019/new/ https://reviews.llvm.org/D65019 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
