nickdesaulniers added inline comments.
================ Comment at: llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp:1922 + const bool Thumb = Opcode == ARM::tBL_PUSHLR; + MachineOperand ReturnAddr = MI.getOperand(0); + assert(ReturnAddr.getReg() == ARM::LR && "expect LR register!"); ---------------- This could be `Register ReturnReg = MI.getOperand(0).getReg();` then the below cleaned up. DRY (and a few more opportunities in the return values of `ARMTargetLowering::LowerINTRINSIC_VOID`) With that change, LGTM, and thank you for the patch! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D65019/new/ https://reviews.llvm.org/D65019 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
