evandro added inline comments.
================ Comment at: llvm/lib/Target/RISCV/RISCVInstrFormats.td:56 +def NoConstraint : RISCVVConstraint<0>; +def WidenV : RISCVVConstraint<1>; +def WidenW : RISCVVConstraint<2>; ---------------- HsiangKai wrote: > evandro wrote: > > HsiangKai wrote: > > > evandro wrote: > > > > Methinks that these constraints `WidenV`, `WidenW`, `WidenCvt`, should > > > > be split up by their components. IOW, into `Widen`, `Wide` (input), > > > > `Cvt`. This way, it's easier to test for specific constraints. > > > Do you mean > > > > > > WidenV = Widen; > > > WidenW = Widen | WideInput; > > > WidenCvt = Widen | Cvt; > > Yes. > Got it. I will improve it based on v0.9 implementation. Please, address this comment before committing. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69987/new/ https://reviews.llvm.org/D69987 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
