[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

[Jessica Clarke via Phabricator via cfe-commits]

jrtc27 added inline comments.


================
Comment at: llvm/include/llvm/Support/RISCVTargetParser.def:22
 PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})
+PROC(SCR1_BASE, {"scr1-base"}, FK_NONE, {"rv32ic"})
+PROC(SCR1_MAX, {"scr1-max"}, FK_NONE, {"rv32imc"})
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Alphabetise (with the exception of INVALID)?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139302/new/

https://reviews.llvm.org/D139302

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