anton-afanasyev added inline comments.
================ Comment at: llvm/lib/Target/RISCV/RISCVSchedSCR1.td:14 +// This model covers SCR1_CFG_RV32IMC_MAX configuration (scr1-max). +// SCR1_CFG_RV32EC_MIN (scr1-min) and SCR1_CFG_RV32IC_BASE (scr1-base) +// configurations have essentially same scheduling characteristics. ---------------- `SCR1_CFG_RV32EC_MIN (scr1-min)` -- this should be removed from comment as well since patch doesn't cover `scr1-min` Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D139302/new/ https://reviews.llvm.org/D139302 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
