eopXD updated this revision to Diff 538012. eopXD marked 3 inline comments as done. eopXD added a comment.
Remove rounding mode variant of vfwcvt.f.f Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154635/new/ https://reviews.llvm.org/D154635 Files: clang/include/clang/Basic/riscv_vector.td clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c llvm/include/llvm/IR/IntrinsicsRISCV.td llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-costrained-sdnode.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll llvm/test/CodeGen/RISCV/rvv/floor-vp.ll llvm/test/CodeGen/RISCV/rvv/fround-costrained-sdnode.ll llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll llvm/test/CodeGen/RISCV/rvv/masked-tama.ll llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll llvm/test/CodeGen/RISCV/rvv/round-vp.ll llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits