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We need unsigned integer here.
Fixes #64534
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D157476
Files:
clang/include/clang/Basic/riscv_vector.td
Index: clang/include/clang/Basic/riscv_vector.td
===================================================================
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -125,7 +125,7 @@
multiclass RVVSlideOneBuiltinSet
: RVVOutOp1BuiltinSet<NAME, "csil",
[["vx", "v", "vve"],
- ["vx", "Uv", "UvUve"]]>;
+ ["vx", "Uv", "UvUvUe"]]>;
multiclass RVVSignedShiftBuiltinSet
: RVVOutOp1BuiltinSet<NAME, "csil",
Index: clang/include/clang/Basic/riscv_vector.td
===================================================================
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -125,7 +125,7 @@
multiclass RVVSlideOneBuiltinSet
: RVVOutOp1BuiltinSet<NAME, "csil",
[["vx", "v", "vve"],
- ["vx", "Uv", "UvUve"]]>;
+ ["vx", "Uv", "UvUvUe"]]>;
multiclass RVVSignedShiftBuiltinSet
: RVVOutOp1BuiltinSet<NAME, "csil",
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