eopXD added a comment. Sorry, my previous comment was wrong. Please allow me to correct myself here.
--- I went through the v-spec again, it says that: > The vslide1up instruction places the x register argument at location 0 of the > destination vector register group, provided that element 0 is active, > otherwise the destination element update follows the current mask > agnostic/undisturbed policy. If XLEN < SEW, the value is sign-extended to SEW > bits. If XLEN > SEW, the least-significant bits are copied over and the high > SEW-XLEN bits are ignored. So I think the righteous fix here is to have the `rs1` parameter as type of `long`, which is to use `l` in the TableGen. --- I still think that modifying the generated test cases is needed. If you find it tedious, may I open up a revision that resolves the problem while adding you as co-author since you gave this problem the first try? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D157476/new/ https://reviews.llvm.org/D157476 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
