aeubanks added a comment.
In D154093#4648931 <https://reviews.llvm.org/D154093#4648931>, @eaeltsin wrote:
> This might have another issue with Verilog -
>
> < import "AAA-BBB" foo bar baz
> ---
> > import {"AAA-",
> > "BBB"} foo bar baz
>
> I wonder if Verilog allows breaking strings in `import`?
From the spec:
`dpi_spec_string ::= "DPI-C" | "DPI"`
Seems like it can't.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D154093/new/
https://reviews.llvm.org/D154093
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