llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang Author: Stefan Pintilie (stefanp-ibm) <details> <summary>Changes</summary> This option already exists on GCC and so it is being added to LLVM so that we use the same option as them. --- Full diff: https://github.com/llvm/llvm-project/pull/70255.diff 8 Files Affected: - (modified) clang/include/clang/Driver/Options.td (+4) - (modified) clang/lib/Basic/Targets/PPC.cpp (+6) - (modified) clang/lib/Basic/Targets/PPC.h (+1) - (added) clang/test/CodeGen/PowerPC/ppc-full-reg-names.c (+78) - (modified) llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp (+9-6) - (modified) llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h (+3-2) - (modified) llvm/lib/Target/PowerPC/PPC.td (+4) - (added) llvm/test/CodeGen/PowerPC/ppc-full-reg-names.ll (+62) ``````````diff diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index e63158fb0e5333a..afb331d2c02c46c 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -4798,6 +4798,10 @@ def mrop_protect : Flag<["-"], "mrop-protect">, Group<m_ppc_Features_Group>; def mprivileged : Flag<["-"], "mprivileged">, Group<m_ppc_Features_Group>; +def mregnames : Flag<["-"], "mregnames">, Group<m_ppc_Features_Group>, + Visibility<[ClangOption]>; +def mno_regnames : Flag<["-"], "mno-regnames">, Group<m_ppc_Features_Group>, + Visibility<[ClangOption]>; } // let Flags = [TargetSpecific] def maix_small_local_exec_tls : Flag<["-"], "maix-small-local-exec-tls">, Group<m_ppc_Features_Group>, diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp index 0d87a3a4e8c20f3..fa8f598c1843461 100644 --- a/clang/lib/Basic/Targets/PPC.cpp +++ b/clang/lib/Basic/Targets/PPC.cpp @@ -89,6 +89,8 @@ bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, IsISA3_1 = true; } else if (Feature == "+quadword-atomics") { HasQuadwordAtomics = true; + } else if (Feature == "+regnames") { + FullRegisterNames = true; } // TODO: Finish this list and add an assert that we've handled them // all. @@ -547,6 +549,9 @@ bool PPCTargetInfo::initFeatureMap( // off by default. Features["aix-small-local-exec-tls"] = false; + // By default full register names are not used in assembly. + Features["regnames"] = false; + Features["spe"] = llvm::StringSwitch<bool>(CPU) .Case("8548", true) .Case("e500", true) @@ -696,6 +701,7 @@ bool PPCTargetInfo::hasFeature(StringRef Feature) const { .Case("isa-v30-instructions", IsISA3_0) .Case("isa-v31-instructions", IsISA3_1) .Case("quadword-atomics", HasQuadwordAtomics) + .Case("regnames", FullRegisterNames) .Default(false); } diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h index 4d62673ba7fb8c5..ddef057bb306cad 100644 --- a/clang/lib/Basic/Targets/PPC.h +++ b/clang/lib/Basic/Targets/PPC.h @@ -80,6 +80,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { bool IsISA3_0 = false; bool IsISA3_1 = false; bool HasQuadwordAtomics = false; + bool FullRegisterNames = false; protected: std::string ABI; diff --git a/clang/test/CodeGen/PowerPC/ppc-full-reg-names.c b/clang/test/CodeGen/PowerPC/ppc-full-reg-names.c new file mode 100644 index 000000000000000..c1bd22c1134c9a7 --- /dev/null +++ b/clang/test/CodeGen/PowerPC/ppc-full-reg-names.c @@ -0,0 +1,78 @@ +// REQUIRES: powerpc-registered-target +// RUN: %clang -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -emit-llvm -mregnames \ +// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=FULLNAMES +// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -emit-llvm -mregnames \ +// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=FULLNAMES +// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -O3 -S -emit-llvm -mregnames \ +// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=FULLNAMES +// RUN: %clang -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -emit-llvm -mno-regnames \ +// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=NOFULLNAMES +// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -emit-llvm -mno-regnames \ +// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=NOFULLNAMES +// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -O3 -S -emit-llvm -mno-regnames \ +// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=NOFULLNAMES + +// Also check the assembly to make sure that the full names are used. +// RUN: %clang -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -mregnames \ +// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=ASMFULLNAMES +// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -mregnames \ +// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=ASMFULLNAMES +// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -O3 -S -mregnames \ +// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=ASMFULLNAMES +// RUN: %clang -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -mno-regnames \ +// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=ASMNOFULLNAMES +// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -O3 -S -mno-regnames \ +// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=ASMNOFULLNAMES +// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -O3 -S -mno-regnames \ +// RUN: -maltivec %s -o - | FileCheck %s --check-prefix=ASMNOFULLNAMES + + + +// FULLNAMES-LABEL: @IntNames +// FULLNAMES-SAME: #0 +// NOFULLNAMES-LABEL: @IntNames +// NOFULLNAMES-SAME: #0 +// ASMFULLNAMES-LABEL: IntNames: +// ASMFULLNAMES: add r3, r4, r3 +// ASMFULLNAMES: blr +// ASMNOFULLNAMES-LABEL: IntNames: +// ASMNOFULLNAMES: add 3, 4, 3 +// ASMNOFULLNAMES: blr +int IntNames(int a, int b) { + return a + b; +} + +// FULLNAMES-LABEL: @FPNames +// FULLNAMES-SAME: #0 +// NOFULLNAMES-LABEL: @FPNames +// NOFULLNAMES-SAME: #0 +// ASMFULLNAMES-LABEL: FPNames: +// ASMFULLNAMES: xsadddp f1, f1, f2 +// ASMFULLNAMES: blr +// ASMNOFULLNAMES-LABEL: FPNames: +// ASMNOFULLNAMES: xsadddp 1, 1, 2 +// ASMNOFULLNAMES: blr +double FPNames(double a, double b) { + return a + b; +} + +// FULLNAMES-LABEL: @VecNames +// FULLNAMES-SAME: #0 +// NOFULLNAMES-LABEL: @VecNames +// NOFULLNAMES-SAME: #0 +// ASMFULLNAMES-LABEL: VecNames: +// ASMFULLNAMES: xvaddsp vs34, vs34, vs35 +// ASMFULLNAMES: blr +// ASMNOFULLNAMES-LABEL: VecNames: +// ASMNOFULLNAMES: xvaddsp 34, 34, 35 +// ASMNOFULLNAMES: blr +vector float VecNames(vector float a, vector float b) { + return a + b; +} + +// FULLNAMES: attributes #0 = { +// FULLNAMES-SAME: +regnames +// NOFULLNAMES: attributes #0 = { +// NOFULLNAMES-SAME: -regnames + + diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp index 0ee7f9f49843172..17498627a84fdfd 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp @@ -614,9 +614,11 @@ bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const { /// getVerboseConditionalRegName - This method expands the condition register /// when requested explicitly or targetting Darwin. const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum, - unsigned RegEncoding) + unsigned RegEncoding, + const MCSubtargetInfo &STI) const { - if (!FullRegNames) + // __SP__ + if (!FullRegNames && !STI.hasFeature(PPC::FeatureFullRegisterNames)) return nullptr; if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN) return nullptr; @@ -635,8 +637,9 @@ const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum, // showRegistersWithPrefix - This method determines whether registers // should be number-only or include the prefix. -bool PPCInstPrinter::showRegistersWithPrefix() const { - return FullRegNamesWithPercent || FullRegNames; +bool PPCInstPrinter::showRegistersWithPrefix(const MCSubtargetInfo &STI) const { + return FullRegNamesWithPercent || FullRegNames || + STI.hasFeature(PPC::FeatureFullRegisterNames); } void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, @@ -648,12 +651,12 @@ void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, Reg = PPC::getRegNumForOperand(MII.get(MI->getOpcode()), Reg, OpNo); const char *RegName; - RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg)); + RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg), STI); if (RegName == nullptr) RegName = getRegisterName(Reg); if (showRegistersWithPercentPrefix(RegName)) O << "%"; - if (!showRegistersWithPrefix()) + if (!showRegistersWithPrefix(STI)) RegName = PPC::stripRegisterPrefix(RegName); O << RegName; diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h index 6ba3eb4c79dc990..2e29971a20fc593 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h @@ -22,9 +22,10 @@ class PPCInstPrinter : public MCInstPrinter { Triple TT; private: bool showRegistersWithPercentPrefix(const char *RegName) const; - bool showRegistersWithPrefix() const; + bool showRegistersWithPrefix(const MCSubtargetInfo &STI) const; const char *getVerboseConditionRegName(unsigned RegNum, - unsigned RegEncoding) const; + unsigned RegEncoding, + const MCSubtargetInfo &STI) const; public: PPCInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td index 535616d33a8032a..568a3d4b5a2aab1 100644 --- a/llvm/lib/Target/PowerPC/PPC.td +++ b/llvm/lib/Target/PowerPC/PPC.td @@ -338,6 +338,10 @@ def FeaturePredictableSelectIsExpensive : def FeatureFastMFLR : SubtargetFeature<"fast-MFLR", "HasFastMFLR", "true", "MFLR is a fast instruction">; +def FeatureFullRegisterNames : + SubtargetFeature<"regnames", "FullRegisterNames", "true", + "Use full register names in assembly.">; + // Since new processors generally contain a superset of features of those that // came before them, the idea is to make implementations of new processors // less error prone and easier to read. diff --git a/llvm/test/CodeGen/PowerPC/ppc-full-reg-names.ll b/llvm/test/CodeGen/PowerPC/ppc-full-reg-names.ll new file mode 100644 index 000000000000000..cb0dcaf7566bcdd --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/ppc-full-reg-names.ll @@ -0,0 +1,62 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-linux-gnu < %s \ +; RUN: -mcpu=pwr8 -mattr=+regnames | FileCheck --check-prefix=FULLNAMES %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-linux-gnu < %s \ +; RUN: -mcpu=pwr8 -mattr=+regnames | FileCheck --check-prefix=FULLNAMES %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff < %s \ +; RUN: -mcpu=pwr8 -mattr=+regnames | FileCheck --check-prefix=FULLNAMES %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-linux-gnu < %s \ +; RUN: -mcpu=pwr8 -mattr=-regnames | FileCheck --check-prefix=NOFULLNAMES %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-linux-gnu < %s \ +; RUN: -mcpu=pwr8 -mattr=-regnames | FileCheck --check-prefix=NOFULLNAMES %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff < %s \ +; RUN: -mcpu=pwr8 -mattr=-regnames | FileCheck --check-prefix=NOFULLNAMES %s + + +define dso_local signext i32 @IntNames(i32 noundef signext %a, i32 noundef signext %b) local_unnamed_addr #0 { +; FULLNAMES-LABEL: IntNames: +; FULLNAMES: # %bb.0: # %entry +; FULLNAMES-NEXT: add r3, r4, r3 +; FULLNAMES-NEXT: extsw r3, r3 +; FULLNAMES-NEXT: blr +; +; NOFULLNAMES-LABEL: IntNames: +; NOFULLNAMES: # %bb.0: # %entry +; NOFULLNAMES-NEXT: add 3, 4, 3 +; NOFULLNAMES-NEXT: extsw 3, 3 +; NOFULLNAMES-NEXT: blr +entry: + %add = add nsw i32 %b, %a + ret i32 %add +} + +define dso_local double @FPNames(double noundef %a, double noundef %b) local_unnamed_addr #0 { +; FULLNAMES-LABEL: FPNames: +; FULLNAMES: # %bb.0: # %entry +; FULLNAMES-NEXT: xsadddp f1, f1, f2 +; FULLNAMES-NEXT: blr +; +; NOFULLNAMES-LABEL: FPNames: +; NOFULLNAMES: # %bb.0: # %entry +; NOFULLNAMES-NEXT: xsadddp 1, 1, 2 +; NOFULLNAMES-NEXT: blr +entry: + %add = fadd double %a, %b + ret double %add +} + +define dso_local <4 x float> @VecNames(<4 x float> noundef %a, <4 x float> noundef %b) local_unnamed_addr #0 { +; FULLNAMES-LABEL: VecNames: +; FULLNAMES: # %bb.0: # %entry +; FULLNAMES-NEXT: xvaddsp vs34, vs34, vs35 +; FULLNAMES-NEXT: blr +; +; NOFULLNAMES-LABEL: VecNames: +; NOFULLNAMES: # %bb.0: # %entry +; NOFULLNAMES-NEXT: xvaddsp 34, 34, 35 +; NOFULLNAMES-NEXT: blr +entry: + %add = fadd <4 x float> %a, %b + ret <4 x float> %add +} + +attributes #0 = { nounwind willreturn "target-features"="+altivec" } `````````` </details> https://github.com/llvm/llvm-project/pull/70255 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits