================ @@ -98,9 +96,34 @@ BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const { for (unsigned n = 0; n < 31; n++) Reserved.set(SP::ASR1 + n); + for (size_t i = 0; i < SP::IntRegsRegClass.getNumRegs() / 4; ++i) { + // Mark both single register and register pairs. + if (MF.getSubtarget<SparcSubtarget>().isGRegisterReserved(i)) { + Reserved.set(SP::G0 + i); + Reserved.set(SP::G0_G1 + i / 2); + } ---------------- s-barannikov wrote:
```suggestion if (MF.getSubtarget<SparcSubtarget>().isGRegisterReserved(i)) markSuperRegs(Reserved, SP::G0 + i); ``` https://github.com/llvm/llvm-project/pull/74927 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits