llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang Author: Djordje Todorovic (djtodoro) <details> <summary>Changes</summary> Depends on https://github.com/llvm/llvm-project/pull/119882. --- Full diff: https://github.com/llvm/llvm-project/pull/119885.diff 7 Files Affected: - (modified) clang/test/Driver/riscv-cpus.c (+17) - (modified) clang/test/Misc/target-invalid-cpu-note/riscv.c (+2) - (modified) llvm/docs/ReleaseNotes.md (+1) - (modified) llvm/lib/Target/RISCV/RISCV.td (+1) - (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+4) - (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+15-1) - (added) llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td (+290) ``````````diff diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 249216612f7ee7..1b09945620f8c3 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -98,6 +98,23 @@ // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=rocket-rv64 | FileCheck -check-prefix=MTUNE-ROCKET64 %s // MTUNE-ROCKET64: "-tune-cpu" "rocket-rv64" +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=mips-p8700 | FileCheck -check-prefix=MTUNE-MIPS-P8700 %s +// MTUNE-MIPS-P8700: "-tune-cpu" "mips-p8700" + +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=mips-p8700 | FileCheck -check-prefix=MCPU-MIPS-P8700 %s +// MCPU-MIPS-P8700: "-target-cpu" "mips-p8700" +// MCPU-MIPS-P8700-SAME: "-target-feature" "+m" +// MCPU-MIPS-P8700-SAME: "-target-feature" "+a" +// MCPU-MIPS-P8700-SAME: "-target-feature" "+f" +// MCPU-MIPS-P8700-SAME: "-target-feature" "+d" +// MCPU-MIPS-P8700-SAME: "-target-feature" "+c" +// MCPU-MIPS-P8700-SAME: "-target-feature" "+zicsr" +// MCPU-MIPS-P8700-SAME: "-target-feature" "+zifencei" +// MCPU-MIPS-P8700-SAME: "-target-feature" "+zaamo" +// MCPU-MIPS-P8700-SAME: "-target-feature" "+zalrsc" +// MCPU-MIPS-P8700-SAME: "-target-feature" "+zba" +// MCPU-MIPS-P8700-SAME: "-target-feature" "+zbb" + // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr1-base | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR1-BASE %s // MTUNE-SYNTACORE-SCR1-BASE: "-tune-cpu" "syntacore-scr1-base" diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c index 8c5df5884cd791..fc8536d99cb804 100644 --- a/clang/test/Misc/target-invalid-cpu-note/riscv.c +++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c @@ -25,6 +25,7 @@ // RISCV64: error: unknown target CPU 'not-a-cpu' // RISCV64-NEXT: note: valid target CPU values are: // RISCV64-SAME: {{^}} generic-rv64 +// RISCV64-SAME: {{^}}, mips-p8700 // RISCV64-SAME: {{^}}, rocket-rv64 // RISCV64-SAME: {{^}}, sifive-p450 // RISCV64-SAME: {{^}}, sifive-p470 @@ -72,6 +73,7 @@ // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu' // TUNE-RISCV64-NEXT: note: valid target CPU values are: // TUNE-RISCV64-SAME: {{^}} generic-rv64 +// TUNE-RISCV64-SAME: {{^}}, mips-p8700 // TUNE-RISCV64-SAME: {{^}}, rocket-rv64 // TUNE-RISCV64-SAME: {{^}}, sifive-p450 // TUNE-RISCV64-SAME: {{^}}, sifive-p470 diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index a5805e050bfdbe..391568b7a3ad3d 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -195,6 +195,7 @@ Changes to the RISC-V Backend * Added `Smctr`, `Ssctr` and `Svvptc` extensions. * `-mcpu=syntacore-scr7` was added. * `-mcpu=tt-ascalon-d8` was added. +* `-mcpu=mips-p8700` was added. * The `Zacas` extension is no longer marked as experimental. * Added Smdbltrp, Ssdbltrp extensions to -march. * The `Smmpm`, `Smnpm`, `Ssnpm`, `Supm`, and `Sspm` pointer masking extensions diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index 00c3d702e12a22..1df6f9ae1944c8 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -46,6 +46,7 @@ include "RISCVMacroFusion.td" // RISC-V Scheduling Models //===----------------------------------------------------------------------===// +include "RISCVSchedMIPSP8700.td" include "RISCVSchedRocket.td" include "RISCVSchedSiFive7.td" include "RISCVSchedSiFiveP400.td" diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 52268c3fa62ccb..3985d83ca075e4 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1477,6 +1477,10 @@ def TuneConditionalCompressedMoveFusion def HasConditionalMoveFusion : Predicate<"Subtarget->hasConditionalMoveFusion()">; def NoConditionalMoveFusion : Predicate<"!Subtarget->hasConditionalMoveFusion()">; +def TuneMIPSP8700 + : SubtargetFeature<"mips-p8700", "RISCVProcFamily", "Others", + "MIPS p8700 processor">; + def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7", "SiFive 7-Series processors">; diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index c4e19c515b155b..9da33e54a05d8b 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -95,6 +95,21 @@ def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64", // to change to the appropriate rv32/rv64 version. def GENERIC : RISCVTuneProcessorModel<"generic", NoSchedModel>, GenericTuneInfo; +def MIPS_P8700 : RISCVProcessorModel<"mips-p8700", + MIPSP8700Model, + [Feature64Bit, + FeatureStdExtI, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZifencei, + FeatureStdExtZicsr], + [TuneMIPSP8700]>; + def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32", RocketModel, [Feature32Bit, @@ -297,7 +312,6 @@ def SIFIVE_P470 : RISCVProcessorModel<"sifive-p470", SiFiveP400Model, [TuneNoSinkSplatOperands, TuneVXRMPipelineFlush])>; - def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model, !listconcat(RVA22U64Features, [FeatureStdExtV, diff --git a/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td b/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td new file mode 100644 index 00000000000000..bf0b1a90c4039c --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td @@ -0,0 +1,290 @@ +//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -----*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// P8700 - a RISC-V processor by MIPS. +// Pipelines: +// - 2 Integer Arithmetic and Logical Units (ALU and AL2) +// - Multiply / Divide Unit (MDU) +// - Branch Unit (CTI) +// - Load Store Unit (LSU) +// - Short Floating Point Pipe (FPUS) +// - Long Floating Point Pipe (FPUL) +//===----------------------------------------------------------------------===// + +def MIPSP8700Model : SchedMachineModel { + int IssueWidth = 4; + int MicroOpBufferSize = 96; + int LoadLatency = 4; + int MispredictPenalty = 8; + let CompleteModel = 0; +} + +let SchedModel = MIPSP8700Model in { +// Handle ALQ Pipelines. +// It contains 1 ALU Unit only. +def p8700ALQ : ProcResource<1> { let BufferSize = 16; } + +// Handle AGQ Pipelines. +def p8700AGQ : ProcResource<3> { let BufferSize = 16; } +def p8700IssueAL2 : ProcResource<1> { let Super = p8700AGQ; } +def p8700IssueCTI : ProcResource<1> { let Super = p8700AGQ; } +def p8700IssueLSU : ProcResource<1> { let Super = p8700AGQ; } +def p8700WriteEitherALU : ProcResGroup<[p8700ALQ, p8700IssueAL2]>; + +// Handle Multiply Divide Pipe. +def p8700GpDiv : ProcResource<1>; +def p8700GpMul : ProcResource<1>; + +let Latency = 1 in { +def : WriteRes<WriteIALU, [p8700WriteEitherALU]>; +def : WriteRes<WriteIALU32, [p8700WriteEitherALU]>; +def : WriteRes<WriteShiftImm, [p8700WriteEitherALU]>; +def : WriteRes<WriteShiftImm32, [p8700WriteEitherALU]>; +def : WriteRes<WriteShiftReg, [p8700WriteEitherALU]>; +def : WriteRes<WriteShiftReg32, [p8700WriteEitherALU]>; + +// Handle zba. +def : WriteRes<WriteSHXADD, [p8700WriteEitherALU]>; +def : WriteRes<WriteSHXADD32, [p8700WriteEitherALU]>; +} + +// Handle zbb. +let Latency = 2 in { +def : WriteRes<WriteCLZ, [p8700IssueAL2]>; +def : WriteRes<WriteCTZ, [p8700IssueAL2]>; +def : WriteRes<WriteCPOP, [p8700IssueAL2]>; +def : WriteRes<WriteCLZ32, [p8700IssueAL2]>; +def : WriteRes<WriteCTZ32, [p8700IssueAL2]>; +def : WriteRes<WriteCPOP32, [p8700IssueAL2]>; +} +let Latency = 1 in { +def : WriteRes<WriteRotateReg, [p8700WriteEitherALU]>; +def : WriteRes<WriteRotateImm, [p8700WriteEitherALU]>; +def : WriteRes<WriteRotateReg32, [p8700WriteEitherALU]>; +def : WriteRes<WriteRotateImm32, [p8700WriteEitherALU]>; +def : WriteRes<WriteREV8, [p8700WriteEitherALU]>; +def : WriteRes<WriteORCB, [p8700WriteEitherALU]>; +def : WriteRes<WriteIMinMax, [p8700WriteEitherALU]>; +} + +let Latency = 0 in { +def : WriteRes<WriteNop, [p8700WriteEitherALU]>; +} + +let Latency = 4 in { +def : WriteRes<WriteLDB, [p8700IssueLSU]>; +def : WriteRes<WriteLDH, [p8700IssueLSU]>; +def : WriteRes<WriteLDW, [p8700IssueLSU]>; +def : WriteRes<WriteLDD, [p8700IssueLSU]>; + +def : WriteRes<WriteAtomicW, [p8700IssueLSU]>; +def : WriteRes<WriteAtomicD, [p8700IssueLSU]>; +def : WriteRes<WriteAtomicLDW, [p8700IssueLSU]>; +def : WriteRes<WriteAtomicLDD, [p8700IssueLSU]>; +} + +let Latency = 8 in { +def : WriteRes<WriteFLD32, [p8700IssueLSU]>; +def : WriteRes<WriteFLD64, [p8700IssueLSU]>; +} + +let Latency = 3 in { +def : WriteRes<WriteSTB, [p8700IssueLSU]>; +def : WriteRes<WriteSTH, [p8700IssueLSU]>; +def : WriteRes<WriteSTW, [p8700IssueLSU]>; +def : WriteRes<WriteSTD, [p8700IssueLSU]>; + +def : WriteRes<WriteAtomicSTW, [p8700IssueLSU]>; +def : WriteRes<WriteAtomicSTD, [p8700IssueLSU]>; +} + +let Latency = 1 in { +def : WriteRes<WriteFST32, [p8700IssueLSU]>; +def : WriteRes<WriteFST64, [p8700IssueLSU]>; +} + +let Latency = 7 in { +def : WriteRes<WriteFMovI32ToF32, [p8700IssueLSU]>; +def : WriteRes<WriteFMovF32ToI32, [p8700IssueLSU]>; +def : WriteRes<WriteFMovI64ToF64, [p8700IssueLSU]>; +def : WriteRes<WriteFMovF64ToI64, [p8700IssueLSU]>; +} + +let Latency = 4 in { +def : WriteRes<WriteIMul, [p8700GpMul]>; +def : WriteRes<WriteIMul32, [p8700GpMul]>; +} + +let Latency = 8, ReleaseAtCycles = [5] in { +def : WriteRes<WriteIDiv, [p8700GpDiv]>; +def : WriteRes<WriteIDiv32, [p8700GpDiv]>; +} + +def : WriteRes<WriteCSR, [p8700ALQ]>; + +def : WriteRes<WriteIRem, []>; +def : WriteRes<WriteIRem32, []>; + +// Handle CTI Pipeline. +let Latency = 1 in { +def : WriteRes<WriteJmp, [p8700IssueCTI]>; +def : WriteRes<WriteJalr, [p8700IssueCTI]>; +} +let Latency = 2 in { +def : WriteRes<WriteJal, [p8700IssueCTI]>; +def : WriteRes<WriteJalr, [p8700IssueCTI]>; +} + +// Handle FPU Pipelines. +def p8700FPQ : ProcResource<3> { let BufferSize = 16; } +def p8700IssueFPUS : ProcResource<1> { let Super = p8700FPQ; } +def p8700IssueFPUL : ProcResource<1> { let Super = p8700FPQ; } +def p8700FpuApu : ProcResource<1>; +def p8700FpuLong : ProcResource<1>; + +let Latency = 4 in { +def : WriteRes<WriteFCvtI32ToF32, [p8700IssueFPUL, p8700FpuApu]>; +def : WriteRes<WriteFCvtI32ToF64, [p8700IssueFPUL, p8700FpuApu]>; +def : WriteRes<WriteFCvtI64ToF32, [p8700IssueFPUL, p8700FpuApu]>; +def : WriteRes<WriteFCvtI64ToF64, [p8700IssueFPUL, p8700FpuApu]>; +def : WriteRes<WriteFCvtF32ToI32, [p8700IssueFPUL, p8700FpuApu]>; +def : WriteRes<WriteFCvtF32ToI64, [p8700IssueFPUL, p8700FpuApu]>; +def : WriteRes<WriteFCvtF32ToF64, [p8700IssueFPUL, p8700FpuApu]>; +def : WriteRes<WriteFCvtF64ToI32, [p8700IssueFPUL, p8700FpuApu]>; +def : WriteRes<WriteFCvtF64ToI64, [p8700IssueFPUL, p8700FpuApu]>; +def : WriteRes<WriteFCvtF64ToF32, [p8700IssueFPUL, p8700FpuApu]>; + +def : WriteRes<WriteFAdd32, [p8700IssueFPUL, p8700FpuApu]>; +def : WriteRes<WriteFAdd64, [p8700IssueFPUL, p8700FpuApu]>; +} + +let Latency = 2 in { +def : WriteRes<WriteFSGNJ32, [p8700IssueFPUS, p8700FpuApu]>; +def : WriteRes<WriteFMinMax32, [p8700IssueFPUS, p8700FpuApu]>; +def : WriteRes<WriteFSGNJ64, [p8700IssueFPUS, p8700FpuApu]>; +def : WriteRes<WriteFMinMax64, [p8700IssueFPUS, p8700FpuApu]>; + +def : WriteRes<WriteFCmp32, [p8700IssueFPUS, p8700FpuApu]>; +def : WriteRes<WriteFCmp64, [p8700IssueFPUS, p8700FpuApu]>; +def : WriteRes<WriteFClass32, [p8700IssueFPUS, p8700FpuApu]>; +def : WriteRes<WriteFClass64, [p8700IssueFPUS, p8700FpuApu]>; +} + +let Latency = 8 in { +def : WriteRes<WriteFMA32, [p8700FpuLong, p8700FpuApu]>; +def : WriteRes<WriteFMA64, [p8700FpuLong, p8700FpuApu]>; +} + +let Latency = 5 in { +def : WriteRes<WriteFMul32, [p8700FpuLong, p8700FpuApu]>; +def : WriteRes<WriteFMul64, [p8700FpuLong, p8700FpuApu]>; +} + +let Latency = 11, ReleaseAtCycles = [1, 11] in { +def : WriteRes<WriteFDiv32, [p8700FpuLong, p8700FpuApu]>; +def : WriteRes<WriteFSqrt32, [p8700FpuLong, p8700FpuApu]>; +} + +let Latency = 17, ReleaseAtCycles = [1, 17] in { +def : WriteRes<WriteFDiv64, [p8700IssueFPUL, p8700FpuApu]>; +def : WriteRes<WriteFSqrt64, [p8700IssueFPUL, p8700FpuApu]>; +} + +// Bypass and advance. +def : ReadAdvance<ReadIALU, 0>; +def : ReadAdvance<ReadIALU32, 0>; +def : ReadAdvance<ReadShiftImm, 0>; +def : ReadAdvance<ReadShiftImm32, 0>; +def : ReadAdvance<ReadShiftReg, 0>; +def : ReadAdvance<ReadShiftReg32, 0>; +def : ReadAdvance<ReadSHXADD, 0>; +def : ReadAdvance<ReadSHXADD32, 0>; +def : ReadAdvance<ReadRotateReg, 0>; +def : ReadAdvance<ReadRotateImm, 0>; +def : ReadAdvance<ReadCLZ, 0>; +def : ReadAdvance<ReadCTZ, 0>; +def : ReadAdvance<ReadCPOP, 0>; +def : ReadAdvance<ReadRotateReg32, 0>; +def : ReadAdvance<ReadRotateImm32, 0>; +def : ReadAdvance<ReadCLZ32, 0>; +def : ReadAdvance<ReadCTZ32, 0>; +def : ReadAdvance<ReadCPOP32, 0>; +def : ReadAdvance<ReadREV8, 0>; +def : ReadAdvance<ReadORCB, 0>; +def : ReadAdvance<ReadIMul, 0>; +def : ReadAdvance<ReadIMul32, 0>; +def : ReadAdvance<ReadIDiv, 0>; +def : ReadAdvance<ReadIDiv32, 0>; +def : ReadAdvance<ReadJmp, 0>; +def : ReadAdvance<ReadJalr, 0>; +def : ReadAdvance<ReadFMovI32ToF32, 0>; +def : ReadAdvance<ReadFMovF32ToI32, 0>; +def : ReadAdvance<ReadFMovI64ToF64, 0>; +def : ReadAdvance<ReadFMovF64ToI64, 0>; +def : ReadAdvance<ReadFSGNJ32, 0>; +def : ReadAdvance<ReadFMinMax32, 0>; +def : ReadAdvance<ReadFSGNJ64, 0>; +def : ReadAdvance<ReadFMinMax64, 0>; +def : ReadAdvance<ReadFCmp32, 0>; +def : ReadAdvance<ReadFCmp64, 0>; +def : ReadAdvance<ReadFCvtI32ToF32, 0>; +def : ReadAdvance<ReadFCvtI32ToF64, 0>; +def : ReadAdvance<ReadFCvtI64ToF32, 0>; +def : ReadAdvance<ReadFCvtI64ToF64, 0>; +def : ReadAdvance<ReadFCvtF32ToI32, 0>; +def : ReadAdvance<ReadFCvtF32ToI64, 0>; +def : ReadAdvance<ReadFCvtF32ToF64, 0>; +def : ReadAdvance<ReadFCvtF64ToI32, 0>; +def : ReadAdvance<ReadFCvtF64ToI64, 0>; +def : ReadAdvance<ReadFCvtF64ToF32, 0>; +def : ReadAdvance<ReadFAdd32, 0>; +def : ReadAdvance<ReadFAdd64, 0>; +def : ReadAdvance<ReadFMul32, 0>; +def : ReadAdvance<ReadFMul64, 0>; +def : ReadAdvance<ReadFMA32, 0>; +def : ReadAdvance<ReadFMA32Addend, 0>; +def : ReadAdvance<ReadFMA64, 0>; +def : ReadAdvance<ReadFMA64Addend, 0>; +def : ReadAdvance<ReadFDiv32, 0>; +def : ReadAdvance<ReadFSqrt32, 0>; +def : ReadAdvance<ReadFDiv64, 0>; +def : ReadAdvance<ReadFSqrt64, 0>; +def : ReadAdvance<ReadAtomicWA, 0>; +def : ReadAdvance<ReadAtomicWD, 0>; +def : ReadAdvance<ReadAtomicDA, 0>; +def : ReadAdvance<ReadAtomicDD, 0>; +def : ReadAdvance<ReadAtomicLDW, 0>; +def : ReadAdvance<ReadAtomicLDD, 0>; +def : ReadAdvance<ReadAtomicSTW, 0>; +def : ReadAdvance<ReadAtomicSTD, 0>; +def : ReadAdvance<ReadFStoreData, 0>; +def : ReadAdvance<ReadCSR, 0>; +def : ReadAdvance<ReadMemBase, 0>; +def : ReadAdvance<ReadStoreData, 0>; +def : ReadAdvance<ReadFMemBase, 0>; +def : ReadAdvance<ReadFClass32, 0>; +def : ReadAdvance<ReadFClass64, 0>; +def : ReadAdvance<ReadIMinMax, 0>; +def : ReadAdvance<ReadIRem, 0>; +def : ReadAdvance<ReadIRem32, 0>; + +// Unsupported extensions. +defm : UnsupportedSchedV; +defm : UnsupportedSchedZbc; +defm : UnsupportedSchedZbs; +defm : UnsupportedSchedZbkb; +defm : UnsupportedSchedZbkx; +defm : UnsupportedSchedZfa; +defm : UnsupportedSchedZfh; +defm : UnsupportedSchedSFB; +defm : UnsupportedSchedZabha; +defm : UnsupportedSchedXsfvcp; +defm : UnsupportedSchedZvk; +defm : UnsupportedSchedZvkned; +} `````````` </details> https://github.com/llvm/llvm-project/pull/119885 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits