================ @@ -0,0 +1,290 @@ +//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -----*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// P8700 - a RISC-V processor by MIPS. +// Pipelines: +// - 2 Integer Arithmetic and Logical Units (ALU and AL2) +// - Multiply / Divide Unit (MDU) +// - Branch Unit (CTI) +// - Load Store Unit (LSU) +// - Short Floating Point Pipe (FPUS) +// - Long Floating Point Pipe (FPUL) +//===----------------------------------------------------------------------===// + +def MIPSP8700Model : SchedMachineModel { + int IssueWidth = 4; + int MicroOpBufferSize = 96; + int LoadLatency = 4; + int MispredictPenalty = 8; + let CompleteModel = 0; +} + +let SchedModel = MIPSP8700Model in { +// Handle ALQ Pipelines. +// It contains 1 ALU Unit only. +def p8700ALQ : ProcResource<1> { let BufferSize = 16; } + +// Handle AGQ Pipelines. +def p8700AGQ : ProcResource<3> { let BufferSize = 16; } +def p8700IssueAL2 : ProcResource<1> { let Super = p8700AGQ; } +def p8700IssueCTI : ProcResource<1> { let Super = p8700AGQ; } +def p8700IssueLSU : ProcResource<1> { let Super = p8700AGQ; } ---------------- mshockwave wrote:
just want to double check: the datasheet says "1 load, 1 store pipe". Are there separate pipes for load and store within a single LSU? https://github.com/llvm/llvm-project/pull/119885 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
