https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/180139
The `Zvabd` is for `RISC-V Integer Vector Absolute Difference` and it provides 5 instructions: * `vabs.v`: Vector Signed Integer Absolute. * `vabd.vv`: Vector Signed Integer Absolute Difference. * `vabdu.vv`: Vector Unsigned Integer Absolute Difference. * `vwabda.vv`: Vector Signed Integer Absolute Difference And Accumulate. * `vwabdau.vv`: Vector Unsigned Integer Absolute Difference And Accumulate. Doc: https://github.com/riscv/integer-vector-absolute-difference >From a9494a760db5e59ef88fe54caad311fb83f6a17f Mon Sep 17 00:00:00 2001 From: Wang Pengcheng <[email protected]> Date: Fri, 6 Feb 2026 16:15:29 +0800 Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?= =?UTF-8?q?l=20version?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Created using spr 1.3.6-beta.1 --- .../Driver/print-supported-extensions-riscv.c | 1 + .../test/Preprocessor/riscv-target-features.c | 9 +++ llvm/docs/RISCVUsage.rst | 3 + llvm/docs/ReleaseNotes.md | 2 + llvm/lib/Target/RISCV/RISCVFeatures.td | 6 ++ llvm/lib/Target/RISCV/RISCVInstrInfo.td | 1 + llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td | 27 ++++++++ llvm/test/CodeGen/RISCV/attributes.ll | 4 ++ llvm/test/CodeGen/RISCV/features-info.ll | 1 + llvm/test/MC/RISCV/rvv/zvabd-invalid.s | 10 +++ llvm/test/MC/RISCV/rvv/zvabd.s | 63 +++++++++++++++++++ .../TargetParser/RISCVISAInfoTest.cpp | 1 + 12 files changed, 128 insertions(+) create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td create mode 100644 llvm/test/MC/RISCV/rvv/zvabd-invalid.s create mode 100644 llvm/test/MC/RISCV/rvv/zvabd.s diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 8337d9f12fabd..3abafb6deafb2 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -245,6 +245,7 @@ // CHECK-NEXT: zibi 0.1 'Zibi' (Branch with Immediate) // CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad) // CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack) +// CHECK-NEXT: zvabd 0.7 'Zvabd' (Vector Absolute Difference) // CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements) // CHECK-NEXT: zvfbfa 0.1 'Zvfbfa' (Additional BF16 vector compute support) // CHECK-NEXT: zvfofp8min 0.2 'Zvfofp8min' (Vector OFP8 Converts) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index e315f75b15614..833a64d23c4e0 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -140,6 +140,7 @@ // CHECK-NOT: __riscv_zkt {{.*$}} // CHECK-NOT: __riscv_zmmul {{.*$}} // CHECK-NOT: __riscv_ztso {{.*$}} +// CHECK-NOT: __riscv_zvabd {{.*$}} // CHECK-NOT: __riscv_zvbb {{.*$}} // CHECK-NOT: __riscv_zvbc {{.*$}} // CHECK-NOT: __riscv_zve32f {{.*$}} @@ -1382,6 +1383,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s // CHECK-ZFA-EXT: __riscv_zfa 1000000{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zve64x_zvabd0p7 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVABD-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_zve64x_zvabd0p7 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVABD-EXT %s +// CHECK-ZVABD-EXT: __riscv_zvabd 7000{{$}} + // RUN: %clang --target=riscv32 \ // RUN: -march=rv32i_zve64x_zvbb1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVBB-EXT %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index b58ecc105620a..6fd52df010991 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -356,6 +356,9 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-smpmpmt`` LLVM implements the `0.6 draft specification <https://github.com/riscv/riscv-isa-manual/blob/smpmpmt/src/smpmpmt.adoc>`__. +``experimental-zvabd`` + LLVM implements the `0.7 draft specification <https://github.com/riscv/integer-vector-absolute-difference/releases/tag/v0.7>`__. + To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`. Vendor Extensions diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 2a535dc0530a0..f9be659ed9bd4 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -129,6 +129,8 @@ Changes to the RISC-V Backend `sspush`, `sspopchk`, `ssrdp`, `c.sspush`, `c.sspopchk`) are now always available in the assembler and disassembler without requiring their respective extensions. +* Adds experimental assembler support for the 'Zvabd` (RISC-V Integer Vector + Absolute Difference) extension. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index e8c8543992865..de7f14802002e 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -688,6 +688,12 @@ def FeatureStdExtV [FeatureStdExtZvl128b, FeatureStdExtZve64d]>, RISCVExtensionBitmask<0, 21>; +def FeatureStdExtZvabd + : RISCVExperimentalExtension<0, 7, "Vector Absolute Difference">; +def HasStdExtZvabd : Predicate<"Subtarget->hasStdExtZvabd()">, + AssemblerPredicate<(all_of FeatureStdExtZvabd), + "'Zvabd' (Vector Absolute Difference)">; + def FeatureStdExtZvfbfa : RISCVExperimentalExtension<0, 1, "Additional BF16 vector compute support", [FeatureStdExtZve32f, FeatureStdExtZfbfmin]>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 156e41ede2d1e..699a1b0bf3cd3 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -2353,6 +2353,7 @@ include "RISCVInstrInfoZk.td" // Vector include "RISCVInstrInfoV.td" +include "RISCVInstrInfoZvabd.td" include "RISCVInstrInfoZvk.td" include "RISCVInstrInfoZvqdotq.td" include "RISCVInstrInfoZvfofp8min.td" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td new file mode 100644 index 0000000000000..b8768f52af399 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td @@ -0,0 +1,27 @@ +//===-- RISCVInstrInfoZvabd.td - 'Zvabd' instructions ------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// This file describes the RISC-V instructions for 'Zvabd' (Vector Absolute +/// Difference). +/// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instruction Definitions +//===----------------------------------------------------------------------===// +let Predicates = [HasStdExtZvabd] in { + defm VABS_V : VALU_MV_VS2<"vabs.v", 0b010010, 0b10000>; + + def VABD_VV : VALUVV<0b010001, OPMVV, "vabd.vv">; + def VABDU_VV : VALUVV<0b010011, OPMVV, "vabdu.vv">; + + let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in { + def VWABDA_VV : VALUVV<0b010101, OPMVV, "vwabda.vv">; + def VWABDAU_VV : VALUVV<0b010110, OPMVV, "vwabdau.vv">; + } // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV +} // Predicates = [HasStdExtZvabd] diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 522dc3579deb1..a17e199eed994 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -111,6 +111,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV32ZVKT %s ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvqdotq %s -o - | FileCheck --check-prefix=RV32ZVQDOTQ %s ; RUN: llc -mtriple=riscv32 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV32ZVFH %s +; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvabd %s -o - | FileCheck --check-prefix=RV32ZVABD %s ; RUN: llc -mtriple=riscv32 -mattr=+zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s ; RUN: llc -mtriple=riscv32 -mattr=+zilsd %s -o - | FileCheck --check-prefix=RV32ZILSD %s ; RUN: llc -mtriple=riscv32 -mattr=+zimop %s -o - | FileCheck --check-prefix=RV32ZIMOP %s @@ -265,6 +266,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV64ZVKT %s ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvqdotq %s -o - | FileCheck --check-prefix=RV64ZVQDOTQ %s ; RUN: llc -mtriple=riscv64 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV64ZVFH %s +; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvabd %s -o - | FileCheck --check-prefix=RV64ZVABD %s ; RUN: llc -mtriple=riscv64 -mattr=+zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s ; RUN: llc -mtriple=riscv64 -mattr=+zimop %s -o - | FileCheck --check-prefix=RV64ZIMOP %s ; RUN: llc -mtriple=riscv64 -mattr=+zcmop %s -o - | FileCheck --check-prefix=RV64ZCMOP %s @@ -430,6 +432,7 @@ ; RV32ZVKT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0" ; RV32ZVQDOTQ: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvqdotq0p0" ; RV32ZVFH: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0" +; RV32ZVABD: .attribute 5, "rv32i2p1_zicsr2p0_zvabd0p7_zve32x1p0_zvl32b1p0" ; RV32ZICOND: .attribute 5, "rv32i2p1_zicond1p0" ; RV32ZILSD: .attribute 5, "rv32i2p1_zilsd1p0" ; RV32ZIMOP: .attribute 5, "rv32i2p1_zimop1p0" @@ -582,6 +585,7 @@ ; RV64ZVKT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0" ; RV64ZVQDOTQ: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvqdotq0p0" ; RV64ZVFH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0" +; RV64ZVABD: .attribute 5, "rv64i2p1_zicsr2p0_zvabd0p7_zve32x1p0_zvl32b1p0" ; RV64ZICOND: .attribute 5, "rv64i2p1_zicond1p0" ; RV64ZIMOP: .attribute 5, "rv64i2p1_zimop1p0" ; RV64ZCMOP: .attribute 5, "rv64i2p1_c2p0_zca1p0_zcmop1p0" diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index 5eadff68895de..c2e56061bf579 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -39,6 +39,7 @@ ; CHECK-NEXT: experimental-zibi - 'Zibi' (Branch with Immediate). ; CHECK-NEXT: experimental-zicfilp - 'Zicfilp' (Landing pad). ; CHECK-NEXT: experimental-zicfiss - 'Zicfiss' (Shadow stack). +; CHECK-NEXT: experimental-zvabd - 'Zvabd' (Vector Absolute Difference). ; CHECK-NEXT: experimental-zvbc32e - 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements). ; CHECK-NEXT: experimental-zvfbfa - 'Zvfbfa' (Additional BF16 vector compute support). ; CHECK-NEXT: experimental-zvfofp8min - 'Zvfofp8min' (Vector OFP8 Converts). diff --git a/llvm/test/MC/RISCV/rvv/zvabd-invalid.s b/llvm/test/MC/RISCV/rvv/zvabd-invalid.s new file mode 100644 index 0000000000000..ec4529b9289cb --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/zvabd-invalid.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple=riscv64 --mattr=+zve64x --mattr=+experimental-zvabd %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +vwabda.vv v9, v9, v8 +# CHECK-ERROR: [[@LINE-1]]:11: error: the destination vector register group cannot overlap the source vector register group +# CHECK-ERROR-LABEL: vwabda.vv v9, v9, v8 + +vwabdau.vv v9, v9, v8 +# CHECK-ERROR: [[@LINE-1]]:12: error: the destination vector register group cannot overlap the source vector register group +# CHECK-ERROR-LABEL: vwabdau.vv v9, v9, v8 diff --git a/llvm/test/MC/RISCV/rvv/zvabd.s b/llvm/test/MC/RISCV/rvv/zvabd.s new file mode 100644 index 0000000000000..2b994ebf94ba6 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/zvabd.s @@ -0,0 +1,63 @@ +# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+v --mattr=+experimental-zvabd %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvabd %s \ +# RUN: | llvm-objdump -d --mattr=+v --mattr=+experimental-zvabd --no-print-imm-hex - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvabd %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vabs.v v9, v8 +# CHECK-INST: vabs.v v9, v8 +# CHECK-ENCODING: [0xd7,0x24,0x88,0x4a] +# CHECK-ERROR: instruction requires the following: 'Zvabd' (Vector Absolute Difference){{$}} +# CHECK-UNKNOWN: 4a8824d7 <unknown> + +vabd.vv v10, v9, v8 +# CHECK-INST: vabd.vv v10, v9, v8 +# CHECK-ENCODING: [0x57,0x25,0x94,0x46] +# CHECK-ERROR: instruction requires the following: 'Zvabd' (Vector Absolute Difference){{$}} +# CHECK-UNKNOWN: 46942557 <unknown> + +vabd.vv v10, v9, v8, v0.t +# CHECK-INST: vabd.vv v10, v9, v8, v0.t +# CHECK-ENCODING: [0x57,0x25,0x94,0x44] +# CHECK-ERROR: instruction requires the following: 'Zvabd' (Vector Absolute Difference){{$}} +# CHECK-UNKNOWN: 44942557 <unknown> + +vabdu.vv v10, v9, v8 +# CHECK-INST: vabdu.vv v10, v9, v8 +# CHECK-ENCODING: [0x57,0x25,0x94,0x4e] +# CHECK-ERROR: instruction requires the following: 'Zvabd' (Vector Absolute Difference){{$}} +# CHECK-UNKNOWN: 4e942557 <unknown> + +vabdu.vv v10, v9, v8, v0.t +# CHECK-INST: vabdu.vv v10, v9, v8, v0.t +# CHECK-ENCODING: [0x57,0x25,0x94,0x4c] +# CHECK-ERROR: instruction requires the following: 'Zvabd' (Vector Absolute Difference){{$}} +# CHECK-UNKNOWN: 4c942557 <unknown> + +vwabda.vv v10, v9, v8 +# CHECK-INST: vwabda.vv v10, v9, v8 +# CHECK-ENCODING: [0x57,0x25,0x94,0x56] +# CHECK-ERROR: instruction requires the following: 'Zvabd' (Vector Absolute Difference){{$}} +# CHECK-UNKNOWN: 56942557 <unknown> + +vwabda.vv v10, v9, v8, v0.t +# CHECK-INST: vwabda.vv v10, v9, v8, v0.t +# CHECK-ENCODING: [0x57,0x25,0x94,0x54] +# CHECK-ERROR: instruction requires the following: 'Zvabd' (Vector Absolute Difference){{$}} +# CHECK-UNKNOWN: 54942557 <unknown> + +vwabdau.vv v10, v9, v8 +# CHECK-INST: vwabdau.vv v10, v9, v8 +# CHECK-ENCODING: [0x57,0x25,0x94,0x5a] +# CHECK-ERROR: instruction requires the following: 'Zvabd' (Vector Absolute Difference){{$}} +# CHECK-UNKNOWN: 5a942557 <unknown> + +vwabdau.vv v10, v9, v8, v0.t +# CHECK-INST: vwabdau.vv v10, v9, v8, v0.t +# CHECK-ENCODING: [0x57,0x25,0x94,0x58] +# CHECK-ERROR: instruction requires the following: 'Zvabd' (Vector Absolute Difference){{$}} +# CHECK-UNKNOWN: 58942557 <unknown> diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index c07551e6cff00..fa09135136889 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1397,6 +1397,7 @@ Experimental extensions zibi 0.1 zicfilp 1.0 This is a long dummy description zicfiss 1.0 + zvabd 0.7 zvbc32e 0.7 zvfbfa 0.1 zvfofp8min 0.2 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
