================ @@ -0,0 +1,27 @@ +//===-- RISCVInstrInfoZvabd.td - 'Zvabd' instructions ------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// This file describes the RISC-V instructions for 'Zvabd' (Vector Absolute +/// Difference). +/// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instruction Definitions +//===----------------------------------------------------------------------===// +let Predicates = [HasStdExtZvabd] in { + defm VABS_V : VALU_MV_VS2<"vabs.v", 0b010010, 0b10000>; ---------------- topperc wrote:
Can we use `VALUVs2<0b010010, 0b10000, OPMVV, "vabs.v">`? VALU_MV_VS2 has the WriteVExtV/ReadVExtV scheduling classes in it which are probably going to be wrong for vabs. VALUVV used by the other instructions in this patch has no scheduling information so using VALUVs2 is consistent. https://github.com/llvm/llvm-project/pull/180139 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
