https://github.com/FantasqueX created https://github.com/llvm/llvm-project/pull/204935
None >From a9a425dd6963bc401fd9c8dc0f01884ab9fb9fb2 Mon Sep 17 00:00:00 2001 From: Letu Ren <[email protected]> Date: Sat, 20 Jun 2026 23:46:06 +0800 Subject: [PATCH] [CIR][RISCV] Support __builtin_riscv_cv_alu_addN --- clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp | 5 ++++- .../CIR/CodeGenBuiltins/RISCV/riscv-xcvalu.c | 22 +++++++++++++++++++ 2 files changed, 26 insertions(+), 1 deletion(-) create mode 100644 clang/test/CIR/CodeGenBuiltins/RISCV/riscv-xcvalu.c diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp index ec262922be942..33876998681cf 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp @@ -168,7 +168,10 @@ CIRGenFunction::emitRISCVBuiltinExpr(unsigned builtinID, const CallExpr *e) { } // XCValu - case RISCV::BI__builtin_riscv_cv_alu_addN: + case RISCV::BI__builtin_riscv_cv_alu_addN: { + intrinsicName = "riscv.cv.alu.addN"; + break; + } case RISCV::BI__builtin_riscv_cv_alu_addRN: case RISCV::BI__builtin_riscv_cv_alu_adduN: case RISCV::BI__builtin_riscv_cv_alu_adduRN: diff --git a/clang/test/CIR/CodeGenBuiltins/RISCV/riscv-xcvalu.c b/clang/test/CIR/CodeGenBuiltins/RISCV/riscv-xcvalu.c new file mode 100644 index 0000000000000..311f0a37ebb90 --- /dev/null +++ b/clang/test/CIR/CodeGenBuiltins/RISCV/riscv-xcvalu.c @@ -0,0 +1,22 @@ +// RUN: %clang_cc1 -triple riscv32 -target-feature +xcvalu -fclangir -emit-cir %s -o - | FileCheck %s --check-prefix=CIR +// RUN: %clang_cc1 -triple riscv32 -target-feature +xcvalu -fclangir -emit-llvm %s -o - | FileCheck %s --check-prefix=LLVM +// RUN: %clang_cc1 -triple riscv32 -target-feature +xcvalu -emit-llvm %s -o - | FileCheck %s --check-prefix=OGCG + +#include <stdint.h> + +// CIR-LABEL: @test_alu_addN( +// CIR: [[C:%.*]] = cir.const #cir.int<0> : !u32i +// CIR: cir.call_llvm_intrinsic "riscv.cv.alu.addN" [[A:%.*]], [[B:%.*]], [[C]] : (!s32i, !s32i, !u32i) -> !s32i +// CIR: cir.return %{{.*}} : !s32i + +// LLVM-LABEL: @test_alu_addN( +// LLVM: call i32 @llvm.riscv.cv.alu.addN(i32 [[A:%.*]], i32 [[B:%.*]], i32 0) +// LLVM: ret i32 + +// OGCG-LABEL: @test_alu_addN( +// OGCG: call i32 @llvm.riscv.cv.alu.addN(i32 [[A:%.*]], i32 [[B:%.*]], i32 0) +// OGCG: ret i32 + +int test_alu_addN(int32_t a, int32_t b) { + return __builtin_riscv_cv_alu_addN(a, b, 0); +} _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
