https://github.com/FantasqueX updated https://github.com/llvm/llvm-project/pull/204935
>From dd3d11b11b89ac02a75bc9703d4134079a030ff1 Mon Sep 17 00:00:00 2001 From: Letu Ren <[email protected]> Date: Sat, 20 Jun 2026 23:46:06 +0800 Subject: [PATCH] [CIR][RISCV] Support XCValu builtins --- clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp | 84 ++++++-- .../CIR/CodeGenBuiltins/RISCV/riscv-xcvalu.c | 183 ++++++++++++++++++ 2 files changed, 251 insertions(+), 16 deletions(-) create mode 100644 clang/test/CIR/CodeGenBuiltins/RISCV/riscv-xcvalu.c diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp index ec262922be942..48f19e0070f0b 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp @@ -168,22 +168,74 @@ CIRGenFunction::emitRISCVBuiltinExpr(unsigned builtinID, const CallExpr *e) { } // XCValu - case RISCV::BI__builtin_riscv_cv_alu_addN: - case RISCV::BI__builtin_riscv_cv_alu_addRN: - case RISCV::BI__builtin_riscv_cv_alu_adduN: - case RISCV::BI__builtin_riscv_cv_alu_adduRN: - case RISCV::BI__builtin_riscv_cv_alu_clip: - case RISCV::BI__builtin_riscv_cv_alu_clipu: - case RISCV::BI__builtin_riscv_cv_alu_extbs: - case RISCV::BI__builtin_riscv_cv_alu_extbz: - case RISCV::BI__builtin_riscv_cv_alu_exths: - case RISCV::BI__builtin_riscv_cv_alu_exthz: - case RISCV::BI__builtin_riscv_cv_alu_sle: - case RISCV::BI__builtin_riscv_cv_alu_sleu: - case RISCV::BI__builtin_riscv_cv_alu_subN: - case RISCV::BI__builtin_riscv_cv_alu_subRN: - case RISCV::BI__builtin_riscv_cv_alu_subuN: - case RISCV::BI__builtin_riscv_cv_alu_subuRN: + case RISCV::BI__builtin_riscv_cv_alu_addN: { + intrinsicName = "riscv.cv.alu.addN"; + break; + } + case RISCV::BI__builtin_riscv_cv_alu_addRN: { + intrinsicName = "riscv.cv.alu.addRN"; + break; + } + case RISCV::BI__builtin_riscv_cv_alu_adduN: { + intrinsicName = "riscv.cv.alu.adduN"; + break; + } + case RISCV::BI__builtin_riscv_cv_alu_adduRN: { + intrinsicName = "riscv.cv.alu.adduRN"; + break; + } + case RISCV::BI__builtin_riscv_cv_alu_clip: { + intrinsicName = "riscv.cv.alu.clip"; + break; + } + case RISCV::BI__builtin_riscv_cv_alu_clipu: { + intrinsicName = "riscv.cv.alu.clipu"; + break; + } + case RISCV::BI__builtin_riscv_cv_alu_extbs: { + mlir::Value result = builder.createIntCast(ops[0], builder.getSInt8Ty()); + return builder.createIntCast(result, returnType); + } + case RISCV::BI__builtin_riscv_cv_alu_extbz: { + mlir::Value result = builder.createIntCast(ops[0], builder.getUInt8Ty()); + return builder.createIntCast(result, returnType); + } + case RISCV::BI__builtin_riscv_cv_alu_exths: { + mlir::Value result = builder.createIntCast(ops[0], builder.getSInt16Ty()); + return builder.createIntCast(result, returnType); + } + case RISCV::BI__builtin_riscv_cv_alu_exthz: { + mlir::Value result = builder.createIntCast(ops[0], builder.getUInt16Ty()); + return builder.createIntCast(result, returnType); + } + case RISCV::BI__builtin_riscv_cv_alu_sle: { + mlir::Location loc = getLoc(e->getSourceRange()); + mlir::Value result = + builder.createCompare(loc, cir::CmpOpKind::le, ops[0], ops[1]); + return builder.createBoolToInt(result, returnType); + } + case RISCV::BI__builtin_riscv_cv_alu_sleu: { + mlir::Location loc = getLoc(e->getSourceRange()); + mlir::Value result = + builder.createCompare(loc, cir::CmpOpKind::le, ops[0], ops[1]); + return builder.createBoolToInt(result, returnType); + } + case RISCV::BI__builtin_riscv_cv_alu_subN: { + intrinsicName = "riscv.cv.alu.subN"; + break; + } + case RISCV::BI__builtin_riscv_cv_alu_subRN: { + intrinsicName = "riscv.cv.alu.subRN"; + break; + } + case RISCV::BI__builtin_riscv_cv_alu_subuN: { + intrinsicName = "riscv.cv.alu.subuN"; + break; + } + case RISCV::BI__builtin_riscv_cv_alu_subuRN: { + intrinsicName = "riscv.cv.alu.subuRN"; + break; + } // XAndesPerf case RISCV::BI__builtin_riscv_nds_ffb_32: case RISCV::BI__builtin_riscv_nds_ffb_64: diff --git a/clang/test/CIR/CodeGenBuiltins/RISCV/riscv-xcvalu.c b/clang/test/CIR/CodeGenBuiltins/RISCV/riscv-xcvalu.c new file mode 100644 index 0000000000000..5f677e5ae730d --- /dev/null +++ b/clang/test/CIR/CodeGenBuiltins/RISCV/riscv-xcvalu.c @@ -0,0 +1,183 @@ +// RUN: %clang_cc1 -triple riscv32 -target-feature +xcvalu -fclangir -emit-cir %s -o - | FileCheck %s --check-prefix=CIR +// RUN: %clang_cc1 -triple riscv32 -target-feature +xcvalu -fclangir -emit-llvm %s -o - | FileCheck %s --check-prefix=LLVM +// RUN: %clang_cc1 -triple riscv32 -target-feature +xcvalu -emit-llvm %s -o - | FileCheck %s --check-prefix=OGCG + +#include <stdint.h> + +// CIR-LABEL: @test_alu_sle( +// CIR: [[CMP:%.*]] = cir.cmp le {{%.*}}, {{%.*}} : !s32i +// CIR: cir.cast bool_to_int [[CMP]] : !cir.bool -> !s32i +// LLVM-LABEL: @test_alu_sle( +// LLVM: [[CMP:%.*]] = icmp sle i32 {{%.*}}, {{%.*}} +// LLVM: zext i1 [[CMP]] to i32 +// OGCG-LABEL: @test_alu_sle( +// OGCG: [[CMP:%.*]] = icmp sle i32 {{%.*}}, {{%.*}} +// OGCG: zext i1 [[CMP]] to i32 +int test_alu_sle(int32_t a, int32_t b) { + return __builtin_riscv_cv_alu_sle(a, b); +} + +// CIR-LABEL: @test_alu_sleu( +// CIR: [[CMP:%.*]] = cir.cmp le {{%.*}}, {{%.*}} : !u32i +// CIR: cir.cast bool_to_int [[CMP]] : !cir.bool -> !s32i +// LLVM-LABEL: @test_alu_sleu( +// LLVM: [[CMP:%.*]] = icmp ule i32 {{%.*}}, {{%.*}} +// LLVM: zext i1 [[CMP]] to i32 +// OGCG-LABEL: @test_alu_sleu( +// OGCG: [[CMP:%.*]] = icmp ule i32 {{%.*}}, {{%.*}} +// OGCG: zext i1 [[CMP]] to i32 +int test_alu_sleu(uint32_t a, uint32_t b) { + return __builtin_riscv_cv_alu_sleu(a, b); +} + +// CIR-LABEL: @test_alu_exths( +// CIR: [[TRUNC:%.*]] = cir.cast integral {{%.*}} : !s32i -> !s16i +// CIR: cir.cast integral [[TRUNC]] : !s16i -> !s32i +// LLVM-LABEL: @test_alu_exths( +// LLVM: [[TRUNC:%.*]] = trunc i32 {{%.*}} to i16 +// LLVM: sext i16 [[TRUNC]] to i32 +// OGCG-LABEL: @test_alu_exths( +// OGCG: [[TRUNC:%.*]] = trunc i32 {{%.*}} to i16 +// OGCG: sext i16 [[TRUNC]] to i32 +int test_alu_exths(int16_t a) { + return __builtin_riscv_cv_alu_exths(a); +} + +// CIR-LABEL: @test_alu_exthz( +// CIR: [[TRUNC:%.*]] = cir.cast integral {{%.*}} : !u32i -> !u16i +// CIR: cir.cast integral [[TRUNC]] : !u16i -> !u32i +// LLVM-LABEL: @test_alu_exthz( +// LLVM: [[TRUNC:%.*]] = trunc i32 {{%.*}} to i16 +// LLVM: zext i16 [[TRUNC]] to i32 +// OGCG-LABEL: @test_alu_exthz( +// OGCG: [[TRUNC:%.*]] = trunc i32 {{%.*}} to i16 +// OGCG: zext i16 [[TRUNC]] to i32 +unsigned int test_alu_exthz(uint16_t a) { + return __builtin_riscv_cv_alu_exthz(a); +} + +// CIR-LABEL: @test_alu_extbs( +// CIR: [[TRUNC:%.*]] = cir.cast integral {{%.*}} : !s32i -> !s8i +// CIR: cir.cast integral [[TRUNC]] : !s8i -> !s32i +// LLVM-LABEL: @test_alu_extbs( +// LLVM: [[TRUNC:%.*]] = trunc i32 {{%.*}} to i8 +// LLVM: sext i8 [[TRUNC]] to i32 +// OGCG-LABEL: @test_alu_extbs( +// OGCG: [[TRUNC:%.*]] = trunc i32 {{%.*}} to i8 +// OGCG: sext i8 [[TRUNC]] to i32 +int test_alu_extbs(int8_t a) { + return __builtin_riscv_cv_alu_extbs(a); +} + +// CIR-LABEL: @test_alu_extbz( +// CIR: [[TRUNC:%.*]] = cir.cast integral {{%.*}} : !u32i -> !u8i +// CIR: cir.cast integral [[TRUNC]] : !u8i -> !u32i +// LLVM-LABEL: @test_alu_extbz( +// LLVM: [[TRUNC:%.*]] = trunc i32 {{%.*}} to i8 +// LLVM: zext i8 [[TRUNC]] to i32 +// OGCG-LABEL: @test_alu_extbz( +// OGCG: [[TRUNC:%.*]] = trunc i32 {{%.*}} to i8 +// OGCG: zext i8 [[TRUNC]] to i32 +unsigned int test_alu_extbz(uint8_t a) { + return __builtin_riscv_cv_alu_extbz(a); +} + +// CIR-LABEL: @test_alu_clip( +// CIR: cir.call_llvm_intrinsic "riscv.cv.alu.clip" {{%.*}}, {{%.*}} : (!s32i, !s32i) -> !s32i +// LLVM-LABEL: @test_alu_clip( +// LLVM: call i32 @llvm.riscv.cv.alu.clip(i32 {{%.*}}, i32 15) +// OGCG-LABEL: @test_alu_clip( +// OGCG: call i32 @llvm.riscv.cv.alu.clip(i32 {{%.*}}, i32 15) +int test_alu_clip(int32_t a) { + return __builtin_riscv_cv_alu_clip(a, 15); +} + +// CIR-LABEL: @test_alu_clipu( +// CIR: cir.call_llvm_intrinsic "riscv.cv.alu.clipu" {{%.*}}, {{%.*}} : (!u32i, !u32i) -> !u32i +// LLVM-LABEL: @test_alu_clipu( +// LLVM: call i32 @llvm.riscv.cv.alu.clipu(i32 {{%.*}}, i32 15) +// OGCG-LABEL: @test_alu_clipu( +// OGCG: call i32 @llvm.riscv.cv.alu.clipu(i32 {{%.*}}, i32 15) +unsigned int test_alu_clipu(uint32_t a) { + return __builtin_riscv_cv_alu_clipu(a, 15); +} + +// CIR-LABEL: @test_alu_addN( +// CIR: cir.call_llvm_intrinsic "riscv.cv.alu.addN" {{%.*}}, {{%.*}}, {{%.*}} : (!s32i, !s32i, !u32i) -> !s32i +// LLVM-LABEL: @test_alu_addN( +// LLVM: call i32 @llvm.riscv.cv.alu.addN(i32 {{%.*}}, i32 {{%.*}}, i32 0) +// OGCG-LABEL: @test_alu_addN( +// OGCG: call i32 @llvm.riscv.cv.alu.addN(i32 {{%.*}}, i32 {{%.*}}, i32 0) +int test_alu_addN(int32_t a, int32_t b) { + return __builtin_riscv_cv_alu_addN(a, b, 0); +} + +// CIR-LABEL: @test_alu_adduN( +// CIR: cir.call_llvm_intrinsic "riscv.cv.alu.adduN" {{%.*}}, {{%.*}}, {{%.*}} : (!u32i, !u32i, !u32i) -> !u32i +// LLVM-LABEL: @test_alu_adduN( +// LLVM: call i32 @llvm.riscv.cv.alu.adduN(i32 {{%.*}}, i32 {{%.*}}, i32 0) +// OGCG-LABEL: @test_alu_adduN( +// OGCG: call i32 @llvm.riscv.cv.alu.adduN(i32 {{%.*}}, i32 {{%.*}}, i32 0) +unsigned int test_alu_adduN(uint32_t a, uint32_t b) { + return __builtin_riscv_cv_alu_adduN(a, b, 0); +} + +// CIR-LABEL: @test_alu_addRN( +// CIR: cir.call_llvm_intrinsic "riscv.cv.alu.addRN" {{%.*}}, {{%.*}}, {{%.*}} : (!s32i, !s32i, !u32i) -> !s32i +// LLVM-LABEL: @test_alu_addRN( +// LLVM: call i32 @llvm.riscv.cv.alu.addRN(i32 {{%.*}}, i32 {{%.*}}, i32 0) +// OGCG-LABEL: @test_alu_addRN( +// OGCG: call i32 @llvm.riscv.cv.alu.addRN(i32 {{%.*}}, i32 {{%.*}}, i32 0) +int test_alu_addRN(int32_t a, int32_t b) { + return __builtin_riscv_cv_alu_addRN(a, b, 0); +} + +// CIR-LABEL: @test_alu_adduRN( +// CIR: cir.call_llvm_intrinsic "riscv.cv.alu.adduRN" {{%.*}}, {{%.*}}, {{%.*}} : (!u32i, !u32i, !u32i) -> !u32i +// LLVM-LABEL: @test_alu_adduRN( +// LLVM: call i32 @llvm.riscv.cv.alu.adduRN(i32 {{%.*}}, i32 {{%.*}}, i32 0) +// OGCG-LABEL: @test_alu_adduRN( +// OGCG: call i32 @llvm.riscv.cv.alu.adduRN(i32 {{%.*}}, i32 {{%.*}}, i32 0) +unsigned int test_alu_adduRN(uint32_t a, uint32_t b) { + return __builtin_riscv_cv_alu_adduRN(a, b, 0); +} + +// CIR-LABEL: @test_alu_subN( +// CIR: cir.call_llvm_intrinsic "riscv.cv.alu.subN" {{%.*}}, {{%.*}}, {{%.*}} : (!s32i, !s32i, !u32i) -> !s32i +// LLVM-LABEL: @test_alu_subN( +// LLVM: call i32 @llvm.riscv.cv.alu.subN(i32 {{%.*}}, i32 {{%.*}}, i32 0) +// OGCG-LABEL: @test_alu_subN( +// OGCG: call i32 @llvm.riscv.cv.alu.subN(i32 {{%.*}}, i32 {{%.*}}, i32 0) +int test_alu_subN(int32_t a, int32_t b) { + return __builtin_riscv_cv_alu_subN(a, b, 0); +} + +// CIR-LABEL: @test_alu_subuN( +// CIR: cir.call_llvm_intrinsic "riscv.cv.alu.subuN" {{%.*}}, {{%.*}}, {{%.*}} : (!u32i, !u32i, !u32i) -> !u32i +// LLVM-LABEL: @test_alu_subuN( +// LLVM: call i32 @llvm.riscv.cv.alu.subuN(i32 {{%.*}}, i32 {{%.*}}, i32 0) +// OGCG-LABEL: @test_alu_subuN( +// OGCG: call i32 @llvm.riscv.cv.alu.subuN(i32 {{%.*}}, i32 {{%.*}}, i32 0) +unsigned int test_alu_subuN(uint32_t a, uint32_t b) { + return __builtin_riscv_cv_alu_subuN(a, b, 0); +} + +// CIR-LABEL: @test_alu_subRN( +// CIR: cir.call_llvm_intrinsic "riscv.cv.alu.subRN" {{%.*}}, {{%.*}}, {{%.*}} : (!s32i, !s32i, !u32i) -> !s32i +// LLVM-LABEL: @test_alu_subRN( +// LLVM: call i32 @llvm.riscv.cv.alu.subRN(i32 {{%.*}}, i32 {{%.*}}, i32 0) +// OGCG-LABEL: @test_alu_subRN( +// OGCG: call i32 @llvm.riscv.cv.alu.subRN(i32 {{%.*}}, i32 {{%.*}}, i32 0) +int test_alu_subRN(int32_t a, int32_t b) { + return __builtin_riscv_cv_alu_subRN(a, b, 0); +} + +// CIR-LABEL: @test_alu_subuRN( +// CIR: cir.call_llvm_intrinsic "riscv.cv.alu.subuRN" {{%.*}}, {{%.*}}, {{%.*}} : (!u32i, !u32i, !u32i) -> !u32i +// LLVM-LABEL: @test_alu_subuRN( +// LLVM: call i32 @llvm.riscv.cv.alu.subuRN(i32 {{%.*}}, i32 {{%.*}}, i32 0) +// OGCG-LABEL: @test_alu_subuRN( +// OGCG: call i32 @llvm.riscv.cv.alu.subuRN(i32 {{%.*}}, i32 {{%.*}}, i32 0) +unsigned int test_alu_subuRN(uint32_t a, uint32_t b) { + return __builtin_riscv_cv_alu_subuRN(a, b, 0); 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