================
@@ -80,6 +80,8 @@ class Triple {
riscv64, // RISC-V (64-bit, little endian): riscv64
riscv32be, // RISC-V (32-bit, big endian): riscv32be
riscv64be, // RISC-V (64-bit, big endian): riscv64be
+ sh, // SuperH (big endian): sh
+ shl, // SuperH (little endian): shl
----------------
LunaTheFoxgirl wrote:
So my suggestion is to essentially enforce the general chip behaviour in the
name, sh4a = sh4a big endian, shl4a = sh4a little endian.
https://github.com/llvm/llvm-project/pull/181287
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