================
@@ -0,0 +1,149 @@
+//===- SuperH.td - Describe the SuperH Target Machine ------*- tablegen
-*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+// This is the top level entry point for the SuperH target.
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Target-independent interfaces
+//===----------------------------------------------------------------------===//
+
+include "llvm/Target/Target.td"
+include "llvm/TableGen/SearchableTable.td"
+
+//===----------------------------------------------------------------------===//
+// SuperH Subtarget features
+//===----------------------------------------------------------------------===//
+
+// NOTE: Some SH4 CPUs support FSCA and FSRRA despite their
+// ISA manuals not specifying so.
+def FeatureFPU : SubtargetFeature<"fp32", "HasFPU", "true",
+ "Enable use of 32-bit floating point
instructions.">;
+def FeatureFPU64 : SubtargetFeature<"fp64", "HasFP64", "true",
+ "Enable use of 64-bit floating point
instructions.",
+ [FeatureFPU]>;
+def FeatureFSCA : SubtargetFeature<"fsca", "HasFSCA", "true",
+ "Enable use of fsca instruction.",
+ [FeatureFPU]>;
+def FeatureFSRRA : SubtargetFeature<"fsrra", "HasFSRRA", "true",
+ "Enable use of fsrra instruction.",
+ [FeatureFPU]>;
+def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true",
+ "Enable SuperH DSP Extensions">;
+
+//===----------------------------------------------------------------------===//
+// SuperH CPU Family features
+//===----------------------------------------------------------------------===//
+
+def FeatureSH2 : SubtargetFeature<"sh2", "SHArchVersion", "SH2",
+ "SH-2 ISA Support",
+ []>;
+def FeatureSH2E : SubtargetFeature<"sh2e", "SHArchVersion", "SH2E",
+ "SH-2E ISA Support",
+ [FeatureSH2, FeatureFPU]>;
+def FeatureSH2A : SubtargetFeature<"sh2a", "SHArchVersion", "SH2A",
+ "SH-2A ISA Support",
+ [FeatureSH2, FeatureFPU, FeatureFPU64]>;
+def FeatureSH3 : SubtargetFeature<"sh3", "SHArchVersion", "SH3",
+ "SH-3 ISA Support",
+ [FeatureSH2]>;
+def FeatureSH3E : SubtargetFeature<"sh3e", "SHArchVersion", "SH3E",
+ "SH-3E ISA Support",
+ [FeatureSH2, FeatureFPU]>;
----------------
alexrp wrote:
Looks like a typo:
```suggestion
[FeatureSH3, FeatureFPU]>;
```
https://github.com/llvm/llvm-project/pull/181287
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