================
@@ -17628,6 +17635,23 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
Results.push_back(DAG.getExtractSubvector(DL, VT, Res, 0));
return;
}
+ case Intrinsic::riscv_psati:
+ case Intrinsic::riscv_pusati: {
+ MVT VT = N->getSimpleValueType(0);
+ if (!Subtarget.is64Bit() || VT != MVT::v2i16)
+ return;
+
+ MVT WideVT = MVT::v4i16;
+ SDValue Rs1 =
+ widenPackedVectorWithZeros(DAG, DL, N->getOperand(1), WideVT);
----------------
sihuan wrote:
We do not. They now use the shared undef widening a few cases above, which
also drops the zext.w on RV64.
https://github.com/llvm/llvm-project/pull/224432
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