================ @@ -2044,6 +2044,13 @@ def riscv_psshar : RVSDNode<"PSSHAR", SDT_RISCVPackedShift>; def riscv_psshl : RVSDNode<"PSSHL", SDT_RISCVPackedShift>; def riscv_psshlr : RVSDNode<"PSSHLR", SDT_RISCVPackedShift>; +// Packed saturation to an immediate width. +def SDT_RISCVPackedSaturation + : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, + SDTCisVT<2, XLenVT>]>; +def riscv_psati : RVSDNode<"PSATI", SDT_RISCVPackedSaturation>; ---------------- sihuan wrote:
Done. The node's immediate is the number of trailing ones in the max value rather than the instruction's width field, so the signed patterns keep IncImm; it is folded into the new sati_widthN/usati_widthN leaves. https://github.com/llvm/llvm-project/pull/224432 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
