https://github.com/MaskRay created https://github.com/llvm/llvm-project/pull/230393
Rename the PowerPC CodeGen options so that they start with ppc-, and turn the -disable-* options into positive options with the default flipped. -enable-ppc-* becomes -ppc-enable-*, and -disable-ppc-ctrloops becomes -ppc-enable-ctrloops, since -ppc-gen-scalar-mass and -ppc-ctrloops are pass names. Preparatory for migrating to LibraryOptions. Aided by Opus 5.5 >From 92e42951c7262865b74e266bef01acdc655bbc11 Mon Sep 17 00:00:00 2001 From: Fangrui Song <[email protected]> Date: Fri, 9 Oct 2026 01:06:12 -0700 Subject: [PATCH] [PowerPC] Prefix option names with ppc-, turn disable- to positive options Rename the PowerPC CodeGen options so that they start with ppc-, and turn the -disable-* options into positive options with the default flipped. -enable-ppc-* becomes -ppc-enable-*, and -disable-ppc-ctrloops becomes -ppc-enable-ctrloops, since -ppc-gen-scalar-mass and -ppc-ctrloops are pass names. Preparatory for migrating to LibraryOptions. Aided by Opus 5.5 --- clang/test/CodeGen/lower-mass-end-to-end.c | 24 +++--- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 6 +- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 5 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 78 +++++++++++-------- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 31 ++++---- .../Target/PowerPC/PPCMachineFunctionInfo.cpp | 10 +-- .../Target/PowerPC/PPCMachineScheduler.cpp | 10 +-- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 10 +-- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp | 62 ++++++++------- .../Target/PowerPC/PPCTargetTransformInfo.cpp | 20 ++--- llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp | 10 +-- .../Analysis/CostModel/PowerPC/load_store.ll | 2 +- .../CodeGen/PowerPC/2006-08-11-RetVector.ll | 4 +- ...009-08-17-inline-asm-addr-mode-breakage.ll | 2 +- .../PowerPC/2011-12-05-NoSpillDupCR.ll | 4 +- llvm/test/CodeGen/PowerPC/addi-licm.ll | 2 +- .../PowerPC/aix-emit-tracebacktable-ssp.ll | 2 +- .../aix-ifunc-toc-restore-query-neg.ll | 2 +- .../PowerPC/aix-ifunc-toc-restore-query.ll | 2 +- llvm/test/CodeGen/PowerPC/branch_coalesce.ll | 4 +- llvm/test/CodeGen/PowerPC/dmrp-spill.ll | 6 +- llvm/test/CodeGen/PowerPC/fma-assoc.ll | 8 +- llvm/test/CodeGen/PowerPC/fma-ext.ll | 4 +- llvm/test/CodeGen/PowerPC/fma-mutate.ll | 2 +- llvm/test/CodeGen/PowerPC/fma.ll | 8 +- llvm/test/CodeGen/PowerPC/lbzux.ll | 2 +- llvm/test/CodeGen/PowerPC/loop-align.ll | 12 +-- .../PowerPC/loop-data-prefetch-inner.ll | 2 +- .../CodeGen/PowerPC/loop-data-prefetch.ll | 2 +- .../PowerPC/lower-intrinsics-afn-mass.ll | 4 +- .../lower-intrinsics-afn-mass_notail.ll | 4 +- .../PowerPC/lower-intrinsics-fast-mass.ll | 4 +- .../lower-intrinsics-fast-mass_notail.ll | 4 +- .../PowerPC/lower-intrinsics-nofast-mass.ll | 4 +- .../CodeGen/PowerPC/lower-scalar-mass-afn.ll | 4 +- .../CodeGen/PowerPC/lower-scalar-mass-fast.ll | 4 +- .../PowerPC/lower-scalar-mass-nofast.ll | 4 +- llvm/test/CodeGen/PowerPC/mma-acc-memops.ll | 8 +- llvm/test/CodeGen/PowerPC/mma-acc-spill.ll | 12 +-- llvm/test/CodeGen/PowerPC/optcmp.ll | 4 +- .../PowerPC/p8altivec-shuffles-pred.ll | 2 +- llvm/test/CodeGen/PowerPC/perfect-shuffle.ll | 4 +- .../pow-025-075-intrinsic-scalar-mass-afn.ll | 4 +- .../pow-025-075-intrinsic-scalar-mass-fast.ll | 4 +- ...ow-025-075-nointrinsic-scalar-mass-fast.ll | 4 +- .../PowerPC/ppc-disable-non-volatile-cr.ll | 2 +- llvm/test/CodeGen/PowerPC/ppc-passname.ll | 4 +- .../PowerPC/ppc64-get-cache-line-size.ll | 14 ++-- .../PowerPC/ppc64-sibcall-shrinkwrap.ll | 10 +-- llvm/test/CodeGen/PowerPC/ppc64-sibcall.ll | 8 +- llvm/test/CodeGen/PowerPC/pr116071.ll | 2 +- llvm/test/CodeGen/PowerPC/prefer-dqform.ll | 4 +- .../CodeGen/PowerPC/schedule-addi-load.mir | 2 +- llvm/test/CodeGen/PowerPC/spill-vec-pair.ll | 4 +- llvm/test/CodeGen/PowerPC/stwu-sched.ll | 4 +- llvm/test/CodeGen/PowerPC/stwu8.ll | 2 +- llvm/test/CodeGen/PowerPC/swaps-le-1.ll | 4 +- .../PowerPC/vec_buildvector_loadstore.ll | 2 +- llvm/test/CodeGen/PowerPC/vec_perf_shuffle.ll | 2 +- llvm/test/CodeGen/PowerPC/vsx-fma-m-early.ll | 12 +-- llvm/test/CodeGen/PowerPC/vsx-fma-m.ll | 4 +- .../LoopDataPrefetch/PowerPC/basic.ll | 2 +- 62 files changed, 256 insertions(+), 236 deletions(-) diff --git a/clang/test/CodeGen/lower-mass-end-to-end.c b/clang/test/CodeGen/lower-mass-end-to-end.c index 41a65900d4d236..d2c82847d43845 100644 --- a/clang/test/CodeGen/lower-mass-end-to-end.c +++ b/clang/test/CodeGen/lower-mass-end-to-end.c @@ -1,18 +1,18 @@ // REQUIRES: powerpc-registered-target -// RUN: %clang -mllvm -enable-ppc-gen-scalar-mass -O3 -fapprox-func --target=powerpc64le-unknown-linux-gnu -S %s -o -| FileCheck %s -check-prefix=CHECK-MASS-AFN -// RUN: %clang -mllvm -enable-ppc-gen-scalar-mass -Ofast --target=powerpc64le-unknown-linux-gnu -S %s -o -| FileCheck %s -check-prefix=CHECK-MASS-FAST -// RUN: %clang -mllvm -enable-ppc-gen-scalar-mass -O3 -fapprox-func --target=powerpc-ibm-aix-xcoff -S %s -o -| FileCheck %s -check-prefix=CHECK-MASS-AFN -// RUN: %clang -mllvm -enable-ppc-gen-scalar-mass -Ofast --target=powerpc-ibm-aix-xcoff -S %s -o -| FileCheck %s -check-prefix=CHECK-MASS-FAST +// RUN: %clang -mllvm -ppc-enable-gen-scalar-mass -O3 -fapprox-func --target=powerpc64le-unknown-linux-gnu -S %s -o -| FileCheck %s -check-prefix=CHECK-MASS-AFN +// RUN: %clang -mllvm -ppc-enable-gen-scalar-mass -Ofast --target=powerpc64le-unknown-linux-gnu -S %s -o -| FileCheck %s -check-prefix=CHECK-MASS-FAST +// RUN: %clang -mllvm -ppc-enable-gen-scalar-mass -O3 -fapprox-func --target=powerpc-ibm-aix-xcoff -S %s -o -| FileCheck %s -check-prefix=CHECK-MASS-AFN +// RUN: %clang -mllvm -ppc-enable-gen-scalar-mass -Ofast --target=powerpc-ibm-aix-xcoff -S %s -o -| FileCheck %s -check-prefix=CHECK-MASS-FAST -// RUN: %clang -mllvm -enable-ppc-gen-scalar-mass=false -O3 -fapprox-func --target=powerpc64le-unknown-linux-gnu -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-AFN -// RUN: %clang -mllvm -enable-ppc-gen-scalar-mass=false -Ofast --target=powerpc64le-unknown-linux-gnu -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-FAST -// RUN: %clang -mllvm -enable-ppc-gen-scalar-mass=false -O3 -fapprox-func --target=powerpc-ibm-aix-xcoff -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-AFN -// RUN: %clang -mllvm -enable-ppc-gen-scalar-mass=false -Ofast --target=powerpc-ibm-aix-xcoff -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-FAST +// RUN: %clang -mllvm -ppc-enable-gen-scalar-mass=false -O3 -fapprox-func --target=powerpc64le-unknown-linux-gnu -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-AFN +// RUN: %clang -mllvm -ppc-enable-gen-scalar-mass=false -Ofast --target=powerpc64le-unknown-linux-gnu -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-FAST +// RUN: %clang -mllvm -ppc-enable-gen-scalar-mass=false -O3 -fapprox-func --target=powerpc-ibm-aix-xcoff -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-AFN +// RUN: %clang -mllvm -ppc-enable-gen-scalar-mass=false -Ofast --target=powerpc-ibm-aix-xcoff -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-FAST -// RUN: %clang -mllvm -enable-ppc-gen-scalar-mass -O3 -fno-approx-func --target=powerpc64le-unknown-linux-gnu -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-AFN -// RUN: %clang -mllvm -enable-ppc-gen-scalar-mass -fno-fast-math --target=powerpc64le-unknown-linux-gnu -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-FAST -// RUN: %clang -mllvm -enable-ppc-gen-scalar-mass -O3 -fno-approx-func --target=powerpc-ibm-aix-xcoff -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-AFN -// RUN: %clang -mllvm -enable-ppc-gen-scalar-mass -fno-fast-math --target=powerpc-ibm-aix-xcoff -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-FAST +// RUN: %clang -mllvm -ppc-enable-gen-scalar-mass -O3 -fno-approx-func --target=powerpc64le-unknown-linux-gnu -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-AFN +// RUN: %clang -mllvm -ppc-enable-gen-scalar-mass -fno-fast-math --target=powerpc64le-unknown-linux-gnu -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-FAST +// RUN: %clang -mllvm -ppc-enable-gen-scalar-mass -O3 -fno-approx-func --target=powerpc-ibm-aix-xcoff -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-AFN +// RUN: %clang -mllvm -ppc-enable-gen-scalar-mass -fno-fast-math --target=powerpc-ibm-aix-xcoff -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-FAST extern double sin(double a); extern double cos(double a); diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp index 0d3275b4b56c5b..e2e3d0f70d0e19 100644 --- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -99,11 +99,11 @@ STATISTIC(NumTOCBlockAddress, "Number of Block Address TOC Entries."); STATISTIC(NumTOCEHBlock, "Number of EH Block TOC Entries."); static cl::opt<bool> EnableSSPCanaryBitInTB( - "aix-ssp-tb-bit", cl::init(false), + "ppc-aix-ssp-tb-bit", cl::init(false), cl::desc("Enable Passing SSP Canary info in Trackback on AIX"), cl::Hidden); static cl::opt<bool> IFuncLocalIfProven( - "ifunc-local-if-proven", cl::init(false), + "ppc-ifunc-local-if-proven", cl::init(false), cl::desc("During ifunc lowering, the compiler assumes the resolver returns " "dso-local functions and bails out if non-local functions are " "detected; this flag flips the assumption: resolver returns " @@ -112,7 +112,7 @@ static cl::opt<bool> IFuncLocalIfProven( cl::Hidden); // this flag is used for testing only as it might generate bad code. -static cl::opt<bool> IFuncWarnInsteadOfError("test-ifunc-warn-noerror", +static cl::opt<bool> IFuncWarnInsteadOfError("ppc-test-ifunc-warn-noerror", cl::init(false), cl::ReallyHidden); // Specialize DenseMapInfo to allow diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index ec276e9880f109..43258d8ff0b879 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -88,8 +88,9 @@ STATISTIC(NumP9Setb, "Number of compares lowered to setb."); // FIXME: Remove this once the bug has been fixed! -cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug", -cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden); +cl::opt<bool> ANDIGlueBug("ppc-expose-andi-glue-bug", + cl::desc("expose the ANDI glue bug on PPC"), + cl::Hidden); static cl::opt<bool> UseBitPermRewriter("ppc-use-bit-perm-rewriter", cl::init(true), diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 05f42551b690f1..25991b74cb599b 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -104,38 +104,45 @@ using namespace llvm; extern cl::opt<bool> EnablePPCGenScalarMASSEntries; -static cl::opt<bool> DisableP10StoreForward( - "disable-p10-store-forward", - cl::desc("disable P10 store forward-friendly conversion"), cl::Hidden, - cl::init(false)); +static cl::opt<bool> EnableP10StoreForward( + "ppc-p10-store-forward", + cl::desc("enable P10 store forward-friendly conversion"), cl::init(true), + cl::Hidden); -static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc", -cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden); +static cl::opt<bool> EnablePPCPreinc( + "ppc-preinc", cl::desc("enable preincrement load/store generation on PPC"), + cl::init(true), cl::Hidden); -static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref", -cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden); +static cl::opt<bool> EnableILPPref( + "ppc-ilp-pref", + cl::desc("enable setting the node scheduling preference to ILP on PPC"), + cl::init(true), cl::Hidden); -static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned", -cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden); +static cl::opt<bool> EnablePPCUnaligned( + "ppc-unaligned", cl::desc("enable unaligned load/store generation on PPC"), + cl::init(true), cl::Hidden); -static cl::opt<bool> DisableSCO("disable-ppc-sco", -cl::desc("disable sibling call optimization on ppc"), cl::Hidden); +static cl::opt<bool> + EnableSCO("ppc-sco", cl::desc("enable sibling call optimization on ppc"), + cl::init(true), cl::Hidden); -static cl::opt<bool> DisableInnermostLoopAlign32("disable-ppc-innermost-loop-align32", -cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden); +static cl::opt<bool> EnableInnermostLoopAlign32( + "ppc-innermost-loop-align32", + cl::desc("always align innermost loop to 32 bytes on ppc"), cl::init(true), + cl::Hidden); static cl::opt<bool> UseAbsoluteJumpTables("ppc-use-absolute-jumptables", cl::desc("use absolute jump tables on ppc"), cl::Hidden); static cl::opt<bool> - DisablePerfectShuffle("ppc-disable-perfect-shuffle", - cl::desc("disable vector permute decomposition"), - cl::init(true), cl::Hidden); + EnablePerfectShuffle("ppc-perfect-shuffle", + cl::desc("enable vector permute decomposition"), + cl::init(false), cl::Hidden); -cl::opt<bool> DisableAutoPairedVecSt( - "disable-auto-paired-vec-st", - cl::desc("disable automatically generated 32byte paired vector stores"), - cl::init(true), cl::Hidden); +cl::opt<bool> EnableAutoPairedVecSt( + "ppc-auto-paired-vec-st", + cl::desc("enable automatically generated 32byte paired vector stores"), + cl::init(false), cl::Hidden); static cl::opt<unsigned> PPCMinimumJumpTableEntries( "ppc-min-jump-table-entries", cl::init(64), cl::Hidden, @@ -1042,7 +1049,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, // LE is P8+/64-bit so direct moves are supported and these operations // are legal. The custom transformation requires 64-bit since we need a // pair of stores that will cover a 128-bit load for P10. - if (!DisableP10StoreForward && isPPC64 && !Subtarget.isLittleEndian()) { + if (EnableP10StoreForward && isPPC64 && !Subtarget.isLittleEndian()) { setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Custom); setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); @@ -1560,8 +1567,8 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, // Enable generation of STXVP instructions by default for mcpu=future. if (CPUDirective == PPC::DIR_PWR_FUTURE && - DisableAutoPairedVecSt.getNumOccurrences() == 0) - DisableAutoPairedVecSt = false; + EnableAutoPairedVecSt.getNumOccurrences() == 0) + EnableAutoPairedVecSt = true; IsStrictFPEnabled = true; @@ -2937,7 +2944,8 @@ bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const { - if (DisablePPCPreinc) return false; + if (!EnablePPCPreinc) + return false; bool isLoad = true; SDValue Ptr; @@ -5018,7 +5026,8 @@ bool PPCTargetLowering::IsEligibleForTailCallOptimization_64SVR4( bool isCalleeExternalSymbol) const { bool TailCallOpt = getTargetMachine().Options.GuaranteedTailCallOpt; - if (DisableSCO && !TailCallOpt) return false; + if (!EnableSCO && !TailCallOpt) + return false; // Variadic argument functions are not supported. if (isVarArg) return false; @@ -5077,7 +5086,8 @@ bool PPCTargetLowering::IsEligibleForTailCallOptimization_64SVR4( if (CalleeCC == CallingConv::Fast && TailCallOpt) return true; - if (DisableSCO) return false; + if (!EnableSCO) + return false; // If callee use the same argument list that caller is using, then we can // apply SCO on this case. If it is not, then we need to check if callee needs @@ -10650,7 +10660,7 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, // perfect shuffle table to emit an optimal matching sequence. ArrayRef<int> PermMask = SVOp->getMask(); - if (!DisablePerfectShuffle && !isLittleEndian) { + if (EnablePerfectShuffle && !isLittleEndian) { unsigned PFIndexes[4]; bool isFourElementShuffle = true; for (unsigned i = 0; i != 4 && isFourElementShuffle; @@ -12103,7 +12113,7 @@ SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, // to avoid load hit store on P10 when running binaries compiled for older // processors by generating two mergeable scalar stores to forward with the // vector load. - if (!DisableP10StoreForward && Subtarget.isPPC64() && + if (EnableP10StoreForward && Subtarget.isPPC64() && !Subtarget.isLittleEndian() && ValVT.isInteger() && ValVT.getSizeInBits() <= 64) { Val = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, Val); @@ -12473,7 +12483,7 @@ SDValue PPCTargetLowering::LowerVectorStore(SDValue Op, // For v256i1 on ISA Future, let the store go through to instruction selection // where it will be matched to stxvp/pstxvp by the instruction patterns. if (StoreVT == MVT::v256i1 && Subtarget.isISAFuture() && - !DisableAutoPairedVecSt) + EnableAutoPairedVecSt) return Op; // For other cases, create 2 or 4 v16i8 stores to store the pair or @@ -18874,7 +18884,7 @@ Align PPCTargetLowering::getPrefLoopAlignment( if (!ML) break; - if (!DisableInnermostLoopAlign32) { + if (EnableInnermostLoopAlign32) { // If the nested loop is an innermost loop, prefer to a 32-byte alignment, // so that we can decrease cache misses and branch-prediction misses. // Actual alignment of the loop will depend on the hotness check and other @@ -19646,7 +19656,7 @@ bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const { bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT, unsigned, Align, MachineMemOperand::Flags, unsigned *Fast) const { - if (DisablePPCUnaligned) + if (!EnablePPCUnaligned) return false; // PowerPC supports unaligned memory access for simple non-vector types. @@ -19817,7 +19827,7 @@ PPCTargetLowering::shouldExpandBuildVectorWithShuffles( } Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const { - if (DisableILPPref || Subtarget.enableMachineScheduler()) + if (!EnableILPPref || Subtarget.enableMachineScheduler()) return TargetLowering::getSchedulingPreference(N); return Sched::ILP; @@ -20489,7 +20499,7 @@ bool PPCTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const { // If sibling calls have been disabled and tail-calls aren't guaranteed // there is no reason to duplicate. auto &TM = getTargetMachine(); - if (!TM.Options.GuaranteedTailCallOpt && DisableSCO) + if (!TM.Options.GuaranteedTailCallOpt && !EnableSCO) return false; // Can't tail call a function called indirectly, or if it has variadic args. diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index 776d7db1abe292..b7b94800ce6e80 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -62,16 +62,21 @@ STATISTIC(MissedConvertibleImmediateInstrs, STATISTIC(NumRcRotatesConvertedToRcAnd, "Number of record-form rotates converted to record-form andi"); -static cl:: -opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden, - cl::desc("Disable analysis for CTR loops")); +static cl::opt<bool> + EnableCTRLoopAnal("ppc-ctrloop-analysis", + cl::desc("Enable analysis for CTR loops"), cl::init(true), + cl::Hidden); -static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt", -cl::desc("Disable compare instruction optimization"), cl::Hidden); +static cl::opt<bool> + EnableCmpOpt("ppc-cmp-opt", + cl::desc("Enable compare instruction optimization"), + cl::init(true), cl::Hidden); -static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy", -cl::desc("Causes the backend to crash instead of generating a nop VSX copy"), -cl::Hidden); +static cl::opt<bool> VSXSelfCopyCrash( + "ppc-crash-on-vsx-self-copy", + cl::desc( + "Causes the backend to crash instead of generating a nop VSX copy"), + cl::Hidden); static cl::opt<bool> UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden, @@ -1324,7 +1329,7 @@ bool PPCInstrInfo::analyzeBranch(MachineBasicBlock &MBB, LastInst.getOpcode() == PPC::BDNZ) { if (!LastInst.getOperand(0).isMBB()) return true; - if (DisableCTRLoopAnal) + if (!EnableCTRLoopAnal) return true; TBB = LastInst.getOperand(0).getMBB(); Cond.push_back(MachineOperand::CreateImm(1)); @@ -1335,7 +1340,7 @@ bool PPCInstrInfo::analyzeBranch(MachineBasicBlock &MBB, LastInst.getOpcode() == PPC::BDZ) { if (!LastInst.getOperand(0).isMBB()) return true; - if (DisableCTRLoopAnal) + if (!EnableCTRLoopAnal) return true; TBB = LastInst.getOperand(0).getMBB(); Cond.push_back(MachineOperand::CreateImm(0)); @@ -1392,7 +1397,7 @@ bool PPCInstrInfo::analyzeBranch(MachineBasicBlock &MBB, if (!SecondLastInst.getOperand(0).isMBB() || !LastInst.getOperand(0).isMBB()) return true; - if (DisableCTRLoopAnal) + if (!EnableCTRLoopAnal) return true; TBB = SecondLastInst.getOperand(0).getMBB(); Cond.push_back(MachineOperand::CreateImm(1)); @@ -1406,7 +1411,7 @@ bool PPCInstrInfo::analyzeBranch(MachineBasicBlock &MBB, if (!SecondLastInst.getOperand(0).isMBB() || !LastInst.getOperand(0).isMBB()) return true; - if (DisableCTRLoopAnal) + if (!EnableCTRLoopAnal) return true; TBB = SecondLastInst.getOperand(0).getMBB(); Cond.push_back(MachineOperand::CreateImm(0)); @@ -2434,7 +2439,7 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const { - if (DisableCmpOpt) + if (!EnableCmpOpt) return false; int OpC = CmpInstr.getOpcode(); diff --git a/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp b/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp index 43c667e7f04aae..f01e9f84e6d778 100644 --- a/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp @@ -14,15 +14,15 @@ #include "llvm/Support/CommandLine.h" using namespace llvm; -static cl::opt<bool> PPCDisableNonVolatileCR( - "ppc-disable-non-volatile-cr", - cl::desc("Disable the use of non-volatile CR register fields"), - cl::init(false), cl::Hidden); +static cl::opt<bool> PPCEnableNonVolatileCR( + "ppc-non-volatile-cr", + cl::desc("Enable the use of non-volatile CR register fields"), + cl::init(true), cl::Hidden); void PPCFunctionInfo::anchor() {} PPCFunctionInfo::PPCFunctionInfo(const Function &F, const TargetSubtargetInfo *STI) - : DisableNonVolatileCR(PPCDisableNonVolatileCR) {} + : DisableNonVolatileCR(!PPCEnableNonVolatileCR) {} MachineFunctionInfo * PPCFunctionInfo::clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, diff --git a/llvm/lib/Target/PowerPC/PPCMachineScheduler.cpp b/llvm/lib/Target/PowerPC/PPCMachineScheduler.cpp index b7e2263424863c..cd6f2ad7fe5f44 100644 --- a/llvm/lib/Target/PowerPC/PPCMachineScheduler.cpp +++ b/llvm/lib/Target/PowerPC/PPCMachineScheduler.cpp @@ -11,10 +11,10 @@ using namespace llvm; -static cl::opt<bool> -DisableAddiLoadHeuristic("disable-ppc-sched-addi-load", - cl::desc("Disable scheduling addi instruction before" - "load for ppc"), cl::Hidden); +static cl::opt<bool> EnableAddiLoadHeuristic( + "ppc-sched-addi-load", + cl::desc("Enable scheduling addi instruction before load for ppc"), + cl::init(true), cl::Hidden); static cl::opt<bool> EnableAddiHeuristic("ppc-postra-bias-addi", cl::desc("Enable scheduling addi instruction as early" @@ -29,7 +29,7 @@ static bool isADDIInstr(const GenericScheduler::SchedCandidate &Cand) { bool PPCPreRASchedStrategy::biasAddiLoadCandidate(SchedCandidate &Cand, SchedCandidate &TryCand, SchedBoundary &Zone) const { - if (DisableAddiLoadHeuristic) + if (!EnableAddiLoadHeuristic) return false; SchedCandidate &FirstCand = Zone.isTop() ? TryCand : Cand; diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp index c2908551402c72..2368c4ffa0d89d 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -88,7 +88,7 @@ ReportAccMoves("ppc-report-acc-moves", cl::Hidden, cl::init(false)); #endif -extern cl::opt<bool> DisableAutoPairedVecSt; +extern cl::opt<bool> EnableAutoPairedVecSt; static unsigned offsetMinAlignForOpcode(unsigned OpC); @@ -1248,11 +1248,11 @@ void PPCRegisterInfo::spillRegPair(MachineBasicBlock &MBB, } /// Remove any STXVP[X] instructions and split them out into a pair of -/// STXV[X] instructions if --disable-auto-paired-vec-st is specified on +/// STXV[X] instructions if --ppc-auto-paired-vec-st=false is specified on /// the command line. void PPCRegisterInfo::lowerOctWordSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const { - assert(DisableAutoPairedVecSt && + assert(!EnableAutoPairedVecSt && "Expecting to do this only if paired vector stores are disabled."); MachineInstr &MI = *II; // STXVP <SrcReg>, <offset> MachineBasicBlock &MBB = *MI.getParent(); @@ -1310,7 +1310,7 @@ void PPCRegisterInfo::lowerACCSpilling(MachineBasicBlock::iterator II, // adjust the offset of the store that is within the 64-byte stack slot. if (IsPrimed) BuildMI(MBB, II, DL, TII.get(PPC::XXMFACC), SrcReg).addReg(SrcReg); - if (DisableAutoPairedVecSt) { + if (!EnableAutoPairedVecSt) { spillRegPair(MBB, II, DL, TII, FrameIndex, IsLittleEndian, IsKilled, TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_pair0), IsLittleEndian ? 48 : 0); @@ -1730,7 +1730,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, lowerACCRestore(II, FrameIndex); return true; case PPC::STXVP: { - if (DisableAutoPairedVecSt) { + if (!EnableAutoPairedVecSt) { lowerOctWordSpilling(II, FrameIndex); return true; } diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp index 32c5f3f20b19d1..501ec270c8c96c 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -49,29 +49,31 @@ using namespace llvm; +static cl::opt<bool> EnableBranchCoalescing( + "ppc-enable-branch-coalesce", cl::Hidden, + cl::desc("enable coalescing of duplicate branches for PPC")); +static cl::opt<bool> EnableCTRLoops("ppc-enable-ctrloops", + cl::desc("Enable CTR loops for PPC"), + cl::init(true), cl::Hidden); static cl::opt<bool> - EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden, - cl::desc("enable coalescing of duplicate branches for PPC")); -static cl:: -opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden, - cl::desc("Disable CTR loops for PPC")); - -static cl:: -opt<bool> DisableInstrFormPrep("disable-ppc-instr-form-prep", cl::Hidden, - cl::desc("Disable PPC loop instr form prep")); + EnableInstrFormPrep("ppc-instr-form-prep", + cl::desc("Enable PPC loop instr form prep"), + cl::init(true), cl::Hidden); static cl::opt<bool> -VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early", - cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early")); + VSXFMAMutateEarly("ppc-schedule-vsx-fma-mutation-early", cl::Hidden, + cl::desc("Schedule VSX FMA instruction mutation early")); -static cl:: -opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden, - cl::desc("Disable VSX Swap Removal for PPC")); +static cl::opt<bool> + EnableVSXSwapRemoval("ppc-vsx-swap-removal", + cl::desc("Enable VSX Swap Removal for PPC"), + cl::init(true), cl::Hidden); -static cl:: -opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden, - cl::desc("Disable machine peepholes for PPC")); +static cl::opt<bool> + EnableMIPeephole("ppc-peephole", + cl::desc("Enable machine peepholes for PPC"), + cl::init(true), cl::Hidden); static cl::opt<bool> EnableGEPOpt("ppc-gep-opt", cl::Hidden, @@ -79,14 +81,14 @@ EnableGEPOpt("ppc-gep-opt", cl::Hidden, cl::init(true)); static cl::opt<bool> -EnablePrefetch("enable-ppc-prefetching", - cl::desc("enable software prefetching on PPC"), - cl::init(false), cl::Hidden); + EnablePrefetch("ppc-enable-prefetching", + cl::desc("enable software prefetching on PPC"), + cl::init(false), cl::Hidden); static cl::opt<bool> -EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps", - cl::desc("Add extra TOC register dependencies"), - cl::init(true), cl::Hidden); + EnableExtraTOCRegDeps("ppc-enable-extra-toc-reg-deps", + cl::desc("Add extra TOC register dependencies"), + cl::init(true), cl::Hidden); static cl::opt<bool> EnableMachineCombinerPass("ppc-machine-combiner", @@ -99,7 +101,7 @@ static cl::opt<bool> cl::init(true), cl::Hidden); cl::opt<bool> EnablePPCGenScalarMASSEntries( - "enable-ppc-gen-scalar-mass", cl::init(false), + "ppc-enable-gen-scalar-mass", cl::init(false), cl::desc("Enable lowering math functions to their corresponding MASS " "(scalar) entries"), cl::Hidden); @@ -450,10 +452,10 @@ bool PPCPassConfig::addPreISel() { addPass(createGlobalMergePass(TM, GlobalMergeMaxOffset, false, false, true, true)); - if (!DisableInstrFormPrep && getOptLevel() != CodeGenOptLevel::None) + if (EnableInstrFormPrep && getOptLevel() != CodeGenOptLevel::None) addPass(createPPCLoopInstrFormPrepPass(getPPCTargetMachine())); - if (!DisableCTRLoops && getOptLevel() != CodeGenOptLevel::None) + if (EnableCTRLoops && getOptLevel() != CodeGenOptLevel::None) addPass(createHardwareLoopsLegacyPass()); return false; @@ -473,7 +475,7 @@ bool PPCPassConfig::addInstSelector() { addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel())); #ifndef NDEBUG - if (!DisableCTRLoops && getOptLevel() != CodeGenOptLevel::None) + if (EnableCTRLoops && getOptLevel() != CodeGenOptLevel::None) addPass(createPPCCTRLoopsVerify()); #endif @@ -484,7 +486,7 @@ bool PPCPassConfig::addInstSelector() { void PPCPassConfig::addMachineSSAOptimization() { // Run CTR loops pass before any cfg modification pass to prevent the // canonical form of hardware loop from being destroied. - if (!DisableCTRLoops && getOptLevel() != CodeGenOptLevel::None) + if (EnableCTRLoops && getOptLevel() != CodeGenOptLevel::None) addPass(createPPCCTRLoopsPass()); // PPCBranchCoalescingPass need to be done before machine sinking @@ -495,14 +497,14 @@ void PPCPassConfig::addMachineSSAOptimization() { // For little endian, remove where possible the vector swap instructions // introduced at code generation to normalize vector element order. if (TM->getTargetTriple().getArch() == Triple::ppc64le && - !DisableVSXSwapRemoval) + EnableVSXSwapRemoval) addPass(createPPCVSXSwapRemovalPass()); // Reduce the number of cr-logical ops. if (ReduceCRLogical && getOptLevel() != CodeGenOptLevel::None) addPass(createPPCReduceCRLogicalsPass()); // Target-specific peephole cleanups performed after instruction // selection. - if (!DisableMIPeephole) { + if (EnableMIPeephole) { addPass(createPPCMIPeepholePass()); addPass(&DeadMachineInstructionElimID); } diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp index 0c14942f839f5f..b7ad26081ea4d9 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp @@ -35,8 +35,10 @@ static cl::opt<bool> Pwr9EVL("ppc-pwr9-evl", static cl::opt<bool> VecMaskCost("ppc-vec-mask-cost", cl::desc("add masking cost for i1 vectors"), cl::init(true), cl::Hidden); -static cl::opt<bool> DisablePPCConstHoist("disable-ppc-constant-hoisting", -cl::desc("disable constant hoisting on PPC"), cl::init(false), cl::Hidden); +static cl::opt<bool> + EnablePPCConstHoist("ppc-constant-hoisting", + cl::desc("enable constant hoisting on PPC"), + cl::init(true), cl::Hidden); static cl::opt<bool> EnablePPCColdCC("ppc-enable-coldcc", cl::Hidden, cl::init(false), @@ -49,10 +51,10 @@ LsrNoInsnsCost("ppc-lsr-no-insns-cost", cl::Hidden, cl::init(false), // The latency of mtctr is only justified if there are more than 4 // comparisons that will be removed as a result. -static cl::opt<unsigned> -SmallCTRLoopThreshold("min-ctr-loop-threshold", cl::init(4), cl::Hidden, - cl::desc("Loops with a constant trip count smaller than " - "this value will not use the count register.")); +static cl::opt<unsigned> SmallCTRLoopThreshold( + "ppc-min-ctr-loop-threshold", cl::init(4), cl::Hidden, + cl::desc("Loops with a constant trip count smaller than " + "this value will not use the count register.")); //===----------------------------------------------------------------------===// // @@ -170,7 +172,7 @@ PPCTTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const { InstructionCost PPCTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const { - if (DisablePPCConstHoist) + if (!EnablePPCConstHoist) return BaseT::getIntImmCost(Imm, Ty, CostKind); assert(Ty->isIntegerTy()); @@ -202,7 +204,7 @@ InstructionCost PPCTTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const { - if (DisablePPCConstHoist) + if (!EnablePPCConstHoist) return BaseT::getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind); assert(Ty->isIntegerTy()); @@ -238,7 +240,7 @@ InstructionCost PPCTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst) const { - if (DisablePPCConstHoist) + if (!EnablePPCConstHoist) return BaseT::getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst); assert(Ty->isIntegerTy()); diff --git a/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp b/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp index 93c541a24b8f07..b538f12ae8cf8c 100644 --- a/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp +++ b/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp @@ -40,10 +40,10 @@ using namespace llvm; // cross-basic-block intervals well. // See: http://lists.llvm.org/pipermail/llvm-dev/2016-February/095669.html // http://reviews.llvm.org/D17087 -static cl::opt<bool> DisableVSXFMAMutate( - "disable-ppc-vsx-fma-mutation", - cl::desc("Disable VSX FMA instruction mutation"), cl::init(true), - cl::Hidden); +static cl::opt<bool> + EnableVSXFMAMutate("ppc-vsx-fma-mutation", + cl::desc("Enable VSX FMA instruction mutation"), + cl::init(false), cl::Hidden); #define DEBUG_TYPE "ppc-vsx-fma-mutate" @@ -339,7 +339,7 @@ namespace { bool Changed = false; - if (DisableVSXFMAMutate) + if (!EnableVSXFMAMutate) return Changed; for (MachineBasicBlock &B : llvm::make_early_inc_range(MF)) diff --git a/llvm/test/Analysis/CostModel/PowerPC/load_store.ll b/llvm/test/Analysis/CostModel/PowerPC/load_store.ll index 167cdf9c333036..85710974875bad 100644 --- a/llvm/test/Analysis/CostModel/PowerPC/load_store.ll +++ b/llvm/test/Analysis/CostModel/PowerPC/load_store.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 -disable-ppc-unaligned | FileCheck %s +; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 -ppc-unaligned=false | FileCheck %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/PowerPC/2006-08-11-RetVector.ll b/llvm/test/CodeGen/PowerPC/2006-08-11-RetVector.ll index a5d4ce9ef247f1..d8c147a3a1aa12 100644 --- a/llvm/test/CodeGen/PowerPC/2006-08-11-RetVector.ll +++ b/llvm/test/CodeGen/PowerPC/2006-08-11-RetVector.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 -ppc-disable-perfect-shuffle=false | grep vsldoi -; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 -ppc-disable-perfect-shuffle=false | not grep vor +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 -ppc-perfect-shuffle | grep vsldoi +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 -ppc-perfect-shuffle | not grep vor ; TODO: Fix this case when disabling perfect shuffle diff --git a/llvm/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll b/llvm/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll index b278da7a140234..8dacfcae8ea3ac 100644 --- a/llvm/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll +++ b/llvm/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -disable-ppc-ilp-pref | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -ppc-ilp-pref=false | FileCheck %s ; ModuleID = '<stdin>' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll b/llvm/test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll index 2c7eeab465bbdf..4a76e1cacf2e0d 100644 --- a/llvm/test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll +++ b/llvm/test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu -mcpu=g4 -disable-ppc-ilp-pref | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g4 -disable-ppc-ilp-pref | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu -mcpu=g4 -ppc-ilp-pref=false | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g4 -ppc-ilp-pref=false | FileCheck %s ; ModuleID = 'tsc.c' target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" diff --git a/llvm/test/CodeGen/PowerPC/addi-licm.ll b/llvm/test/CodeGen/PowerPC/addi-licm.ll index f59c886425f808..2d195c0fbb7658 100644 --- a/llvm/test/CodeGen/PowerPC/addi-licm.ll +++ b/llvm/test/CodeGen/PowerPC/addi-licm.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -disable-ppc-instr-form-prep < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-instr-form-prep=false < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PIP target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-ssp.ll b/llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-ssp.ll index f45dc271f85469..dd2abbfe37bc78 100644 --- a/llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-ssp.ll +++ b/llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-ssp.ll @@ -1,4 +1,4 @@ -; RUN: llc -aix-ssp-tb-bit -mtriple=powerpc64-ibm-aix-xcoff --code-model=small -O0 < %s | FileCheck %s +; RUN: llc -ppc-aix-ssp-tb-bit -mtriple=powerpc64-ibm-aix-xcoff --code-model=small -O0 < %s | FileCheck %s ; CHECK-LABEL: f: ; CHECK: __ssp_canary_word diff --git a/llvm/test/CodeGen/PowerPC/aix-ifunc-toc-restore-query-neg.ll b/llvm/test/CodeGen/PowerPC/aix-ifunc-toc-restore-query-neg.ll index 221b29c7614c3e..2d2bdb6223b970 100644 --- a/llvm/test/CodeGen/PowerPC/aix-ifunc-toc-restore-query-neg.ll +++ b/llvm/test/CodeGen/PowerPC/aix-ifunc-toc-restore-query-neg.ll @@ -2,7 +2,7 @@ ; This testcase is for testing the negative return values of the ; TOCRestoreNeededForCallToImplementation query. -; RUN: llc < %s -mtriple=powerpc64-ibm-aix-xcoff -test-ifunc-warn-noerror -filetype=obj -o /dev/null 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-ibm-aix-xcoff -ppc-test-ifunc-warn-noerror -filetype=obj -o /dev/null 2>&1 | FileCheck %s ; CHECK: TOC register save/restore needed for ifunc "foo_ext_decl_ifunc" ; CHECK: TOC register save/restore needed for ifunc "foo_ext_default_decl_ifunc" diff --git a/llvm/test/CodeGen/PowerPC/aix-ifunc-toc-restore-query.ll b/llvm/test/CodeGen/PowerPC/aix-ifunc-toc-restore-query.ll index 20d24d30db855f..57ae2b638dec78 100644 --- a/llvm/test/CodeGen/PowerPC/aix-ifunc-toc-restore-query.ll +++ b/llvm/test/CodeGen/PowerPC/aix-ifunc-toc-restore-query.ll @@ -5,7 +5,7 @@ ; REQUIRES: asserts ; RUN: llc < %s -mtriple=powerpc64-ibm-aix-xcoff --function-sections -filetype=obj -o /dev/null -debug-only=asmprinter 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=powerpc-ibm-aix-xcoff --function-sections -filetype=obj -o /dev/null -debug-only=asmprinter 2>&1 | FileCheck %s -; RUN: llc < %s -mtriple=powerpc64-ibm-aix-xcoff -ifunc-local-if-proven=1 -o /dev/null -debug-only=asmprinter 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-ibm-aix-xcoff -ppc-ifunc-local-if-proven=1 -o /dev/null -debug-only=asmprinter 2>&1 | FileCheck %s ; CHECK: foo_ext_hidden_decl is dso_local ; CHECK: foo_ext_hidden_def is dso_local diff --git a/llvm/test/CodeGen/PowerPC/branch_coalesce.ll b/llvm/test/CodeGen/PowerPC/branch_coalesce.ll index 61d6ef5a9d48b7..2e4187256c4e9b 100644 --- a/llvm/test/CodeGen/PowerPC/branch_coalesce.ll +++ b/llvm/test/CodeGen/PowerPC/branch_coalesce.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs -enable-ppc-branch-coalesce < %s | FileCheck %s -; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs -enable-ppc-branch-coalesce < %s | FileCheck %s +; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs -ppc-enable-branch-coalesce < %s | FileCheck %s +; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs -ppc-enable-branch-coalesce < %s | FileCheck %s ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOCOALESCE %s ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOCOALESCE %s diff --git a/llvm/test/CodeGen/PowerPC/dmrp-spill.ll b/llvm/test/CodeGen/PowerPC/dmrp-spill.ll index 88afec18f7b1d3..8038fba56ada65 100644 --- a/llvm/test/CodeGen/PowerPC/dmrp-spill.ll +++ b/llvm/test/CodeGen/PowerPC/dmrp-spill.ll @@ -1,12 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ -; RUN: -disable-auto-paired-vec-st=false -ppc-asm-full-reg-names \ +; RUN: -ppc-auto-paired-vec-st -ppc-asm-full-reg-names \ ; RUN: -ppc-vsr-nums-as-vr -mcpu=future < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \ -; RUN: -disable-auto-paired-vec-st=false -ppc-asm-full-reg-names \ +; RUN: -ppc-auto-paired-vec-st -ppc-asm-full-reg-names \ ; RUN: -ppc-vsr-nums-as-vr -mcpu=future < %s | FileCheck %s --check-prefix=AIX ; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \ -; RUN: -disable-auto-paired-vec-st=false -ppc-asm-full-reg-names \ +; RUN: -ppc-auto-paired-vec-st -ppc-asm-full-reg-names \ ; RUN: -ppc-vsr-nums-as-vr -mcpu=future < %s | FileCheck %s --check-prefix=AIX32 declare void @dummy_func() diff --git a/llvm/test/CodeGen/PowerPC/fma-assoc.ll b/llvm/test/CodeGen/PowerPC/fma-assoc.ll index 8a3d5deaf3069e..a81265d876262b 100644 --- a/llvm/test/CodeGen/PowerPC/fma-assoc.ll +++ b/llvm/test/CodeGen/PowerPC/fma-assoc.ll @@ -1,13 +1,13 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- \ -; RUN: -mcpu=ppc -mattr=-vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s +; RUN: -mcpu=ppc -mattr=-vsx -ppc-vsx-fma-mutation | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-ibm-aix-xcoff \ -; RUN: -mcpu=ppc -mattr=-vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s +; RUN: -mcpu=ppc -mattr=-vsx -ppc-vsx-fma-mutation | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \ -; RUN: -mattr=+vsx -disable-ppc-vsx-fma-mutation=false \ +; RUN: -mattr=+vsx -ppc-vsx-fma-mutation \ ; RUN: -mcpu=pwr7 | FileCheck -check-prefix=CHECK-VSX %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff \ -; RUN: -mattr=+vsx -disable-ppc-vsx-fma-mutation=false \ +; RUN: -mattr=+vsx -ppc-vsx-fma-mutation \ ; RUN: -mcpu=pwr7 -target-abi=vec-extabi | FileCheck -check-prefix=CHECK-VSX %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpcspe-linux-unknown-gnu \ ; RUN: | FileCheck -check-prefix=CHECK-SPE %s diff --git a/llvm/test/CodeGen/PowerPC/fma-ext.ll b/llvm/test/CodeGen/PowerPC/fma-ext.ll index 494bb8cfe34b55..45dcef2b187462 100644 --- a/llvm/test/CodeGen/PowerPC/fma-ext.ll +++ b/llvm/test/CodeGen/PowerPC/fma-ext.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mattr=-vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -mcpu=pwr7 -disable-ppc-vsx-fma-mutation=false | FileCheck -check-prefix=CHECK-VSX %s +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mattr=-vsx -ppc-vsx-fma-mutation | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -mcpu=pwr7 -ppc-vsx-fma-mutation | FileCheck -check-prefix=CHECK-VSX %s define double @test_FMADD_EXT1(float %A, float %B, double %C) { %D = fmul contract float %A, %B ; <float> [#uses=1] diff --git a/llvm/test/CodeGen/PowerPC/fma-mutate.ll b/llvm/test/CodeGen/PowerPC/fma-mutate.ll index c2f764b9d6ef41..5168896f4f421a 100644 --- a/llvm/test/CodeGen/PowerPC/fma-mutate.ll +++ b/llvm/test/CodeGen/PowerPC/fma-mutate.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx -ppc-vsx-fma-mutation | FileCheck %s declare double @llvm.sqrt.f64(double) diff --git a/llvm/test/CodeGen/PowerPC/fma.ll b/llvm/test/CodeGen/PowerPC/fma.ll index 993746c0b51bdb..5000d973ddfb22 100644 --- a/llvm/test/CodeGen/PowerPC/fma.ll +++ b/llvm/test/CodeGen/PowerPC/fma.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mattr=-vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -mcpu=pwr7 -disable-ppc-vsx-fma-mutation=false | FileCheck -check-prefix=CHECK-VSX %s -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -disable-ppc-vsx-fma-mutation=false | FileCheck -check-prefix=CHECK-P8 %s -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -disable-ppc-vsx-fma-mutation=false | FileCheck -check-prefix=CHECK-P8 %s +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mattr=-vsx -ppc-vsx-fma-mutation | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -mcpu=pwr7 -ppc-vsx-fma-mutation | FileCheck -check-prefix=CHECK-VSX %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -ppc-vsx-fma-mutation | FileCheck -check-prefix=CHECK-P8 %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ppc-vsx-fma-mutation | FileCheck -check-prefix=CHECK-P8 %s declare double @dummy1(double) #0 declare double @dummy2(double, double) #0 diff --git a/llvm/test/CodeGen/PowerPC/lbzux.ll b/llvm/test/CodeGen/PowerPC/lbzux.ll index fed5a5f3f5052c..0e8aa02bfe149b 100644 --- a/llvm/test/CodeGen/PowerPC/lbzux.ll +++ b/llvm/test/CodeGen/PowerPC/lbzux.ll @@ -1,6 +1,6 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" -; RUN: llc -verify-machineinstrs -disable-ppc-unaligned < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -ppc-unaligned=false < %s | FileCheck %s define fastcc void @allocateSpace(i1 %cond1, i1 %cond2, i32 %offset) nounwind { entry: diff --git a/llvm/test/CodeGen/PowerPC/loop-align.ll b/llvm/test/CodeGen/PowerPC/loop-align.ll index 0ad68df635694f..d0a6e7db55dcac 100644 --- a/llvm/test/CodeGen/PowerPC/loop-align.ll +++ b/llvm/test/CodeGen/PowerPC/loop-align.ll @@ -5,12 +5,12 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR -; Test the loop alignment and the option -disable-ppc-innermost-loop-align32. -; RUN: llc -verify-machineinstrs -mcpu=a2 -disable-ppc-innermost-loop-align32 -mtriple powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,GENERIC-DISABLE-PPC-INNERMOST-LOOP-ALIGN32 -; RUN: llc -verify-machineinstrs -mcpu=pwr8 -disable-ppc-innermost-loop-align32 -mtriple powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR-DISABLE-PPC-INNERMOST-LOOP-ALIGN32 -; RUN: llc -verify-machineinstrs -mcpu=pwr9 -disable-ppc-innermost-loop-align32 -mtriple powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR-DISABLE-PPC-INNERMOST-LOOP-ALIGN32 -; RUN: llc -verify-machineinstrs -mcpu=pwr8 -disable-ppc-innermost-loop-align32 -mtriple powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR-DISABLE-PPC-INNERMOST-LOOP-ALIGN32 -; RUN: llc -verify-machineinstrs -mcpu=pwr9 -disable-ppc-innermost-loop-align32 -mtriple powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR-DISABLE-PPC-INNERMOST-LOOP-ALIGN32 +; Test the loop alignment and the option -ppc-innermost-loop-align32=false. +; RUN: llc -verify-machineinstrs -mcpu=a2 -ppc-innermost-loop-align32=false -mtriple powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,GENERIC-DISABLE-PPC-INNERMOST-LOOP-ALIGN32 +; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-innermost-loop-align32=false -mtriple powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR-DISABLE-PPC-INNERMOST-LOOP-ALIGN32 +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-innermost-loop-align32=false -mtriple powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR-DISABLE-PPC-INNERMOST-LOOP-ALIGN32 +; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-innermost-loop-align32=false -mtriple powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR-DISABLE-PPC-INNERMOST-LOOP-ALIGN32 +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-innermost-loop-align32=false -mtriple powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR-DISABLE-PPC-INNERMOST-LOOP-ALIGN32 %struct.parm = type { ptr, i32, i32 } diff --git a/llvm/test/CodeGen/PowerPC/loop-data-prefetch-inner.ll b/llvm/test/CodeGen/PowerPC/loop-data-prefetch-inner.ll index 9c80bfd62b2b42..528c8e37e8f0b4 100644 --- a/llvm/test/CodeGen/PowerPC/loop-data-prefetch-inner.ll +++ b/llvm/test/CodeGen/PowerPC/loop-data-prefetch-inner.ll @@ -1,4 +1,4 @@ -; RUN: llc -enable-ppc-prefetching=true -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -ppc-enable-prefetching=true -verify-machineinstrs < %s | FileCheck %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64le-unknown-linux" diff --git a/llvm/test/CodeGen/PowerPC/loop-data-prefetch.ll b/llvm/test/CodeGen/PowerPC/loop-data-prefetch.ll index 7127519e97c53d..603025a218ae36 100644 --- a/llvm/test/CodeGen/PowerPC/loop-data-prefetch.ll +++ b/llvm/test/CodeGen/PowerPC/loop-data-prefetch.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -enable-ppc-prefetching=true -mcpu=a2 < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -ppc-enable-prefetching=true -mcpu=a2 < %s | FileCheck %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64le-unknown-linux" diff --git a/llvm/test/CodeGen/PowerPC/lower-intrinsics-afn-mass.ll b/llvm/test/CodeGen/PowerPC/lower-intrinsics-afn-mass.ll index 6ae851161c12d7..ab5d11aade9975 100644 --- a/llvm/test/CodeGen/PowerPC/lower-intrinsics-afn-mass.ll +++ b/llvm/test/CodeGen/PowerPC/lower-intrinsics-afn-mass.ll @@ -1,5 +1,5 @@ -; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck %s +; RUN: llc -ppc-enable-gen-scalar-mass -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s +; RUN: llc -ppc-enable-gen-scalar-mass -O3 -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck %s declare float @llvm.cos.f32(float) declare float @llvm.exp.f32(float) diff --git a/llvm/test/CodeGen/PowerPC/lower-intrinsics-afn-mass_notail.ll b/llvm/test/CodeGen/PowerPC/lower-intrinsics-afn-mass_notail.ll index a4a5a6ac992e47..8fc0802bab0ce6 100644 --- a/llvm/test/CodeGen/PowerPC/lower-intrinsics-afn-mass_notail.ll +++ b/llvm/test/CodeGen/PowerPC/lower-intrinsics-afn-mass_notail.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck --check-prefix=CHECK-LNX %s -; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mcpu=ppc -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefix=CHECK-AIX %s +; RUN: llc -ppc-enable-gen-scalar-mass -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck --check-prefix=CHECK-LNX %s +; RUN: llc -ppc-enable-gen-scalar-mass -O3 -mcpu=ppc -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefix=CHECK-AIX %s define void @cos_f64(ptr %arg) { ; CHECK-LNX-LABEL: cos_f64: diff --git a/llvm/test/CodeGen/PowerPC/lower-intrinsics-fast-mass.ll b/llvm/test/CodeGen/PowerPC/lower-intrinsics-fast-mass.ll index f5adace09b293f..0e5d445410b566 100644 --- a/llvm/test/CodeGen/PowerPC/lower-intrinsics-fast-mass.ll +++ b/llvm/test/CodeGen/PowerPC/lower-intrinsics-fast-mass.ll @@ -1,5 +1,5 @@ -; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck %s +; RUN: llc -ppc-enable-gen-scalar-mass -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s +; RUN: llc -ppc-enable-gen-scalar-mass -O3 -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck %s declare float @llvm.cos.f32(float) declare float @llvm.exp.f32(float) diff --git a/llvm/test/CodeGen/PowerPC/lower-intrinsics-fast-mass_notail.ll b/llvm/test/CodeGen/PowerPC/lower-intrinsics-fast-mass_notail.ll index 55de4e200cf5ec..f11b606797355f 100644 --- a/llvm/test/CodeGen/PowerPC/lower-intrinsics-fast-mass_notail.ll +++ b/llvm/test/CodeGen/PowerPC/lower-intrinsics-fast-mass_notail.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck --check-prefix=CHECK-LNX %s -; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mcpu=ppc -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefix=CHECK-AIX %s +; RUN: llc -ppc-enable-gen-scalar-mass -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck --check-prefix=CHECK-LNX %s +; RUN: llc -ppc-enable-gen-scalar-mass -O3 -mcpu=ppc -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefix=CHECK-AIX %s define void @cos_f64(ptr %arg) { ; CHECK-LNX-LABEL: cos_f64: diff --git a/llvm/test/CodeGen/PowerPC/lower-intrinsics-nofast-mass.ll b/llvm/test/CodeGen/PowerPC/lower-intrinsics-nofast-mass.ll index 3d6e6da3b66d9a..d623c692e6f270 100644 --- a/llvm/test/CodeGen/PowerPC/lower-intrinsics-nofast-mass.ll +++ b/llvm/test/CodeGen/PowerPC/lower-intrinsics-nofast-mass.ll @@ -1,5 +1,5 @@ -; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck %s +; RUN: llc -ppc-enable-gen-scalar-mass -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s +; RUN: llc -ppc-enable-gen-scalar-mass -O3 -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck %s declare float @llvm.cos.f32(float) declare float @llvm.exp.f32(float) diff --git a/llvm/test/CodeGen/PowerPC/lower-scalar-mass-afn.ll b/llvm/test/CodeGen/PowerPC/lower-scalar-mass-afn.ll index f3085ccc85c88e..a3b8548ea74ee1 100644 --- a/llvm/test/CodeGen/PowerPC/lower-scalar-mass-afn.ll +++ b/llvm/test/CodeGen/PowerPC/lower-scalar-mass-afn.ll @@ -1,5 +1,5 @@ -; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck %s +; RUN: llc -ppc-enable-gen-scalar-mass -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s +; RUN: llc -ppc-enable-gen-scalar-mass -O3 -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck %s declare float @acosf (float); declare float @acoshf (float); diff --git a/llvm/test/CodeGen/PowerPC/lower-scalar-mass-fast.ll b/llvm/test/CodeGen/PowerPC/lower-scalar-mass-fast.ll index 8c22d43040d36f..e0261e6df25853 100644 --- a/llvm/test/CodeGen/PowerPC/lower-scalar-mass-fast.ll +++ b/llvm/test/CodeGen/PowerPC/lower-scalar-mass-fast.ll @@ -1,5 +1,5 @@ -; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck %s +; RUN: llc -ppc-enable-gen-scalar-mass -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s +; RUN: llc -ppc-enable-gen-scalar-mass -O3 -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck %s declare float @acosf (float); declare float @acoshf (float); diff --git a/llvm/test/CodeGen/PowerPC/lower-scalar-mass-nofast.ll b/llvm/test/CodeGen/PowerPC/lower-scalar-mass-nofast.ll index 6624b5752139c9..e38a4a7f13507d 100644 --- a/llvm/test/CodeGen/PowerPC/lower-scalar-mass-nofast.ll +++ b/llvm/test/CodeGen/PowerPC/lower-scalar-mass-nofast.ll @@ -1,5 +1,5 @@ -; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck %s +; RUN: llc -ppc-enable-gen-scalar-mass -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s +; RUN: llc -ppc-enable-gen-scalar-mass -O3 -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck %s declare float @acosf (float); declare float @acoshf (float); diff --git a/llvm/test/CodeGen/PowerPC/mma-acc-memops.ll b/llvm/test/CodeGen/PowerPC/mma-acc-memops.ll index 8d600ea209f193..63bc307126ba37 100644 --- a/llvm/test/CodeGen/PowerPC/mma-acc-memops.ll +++ b/llvm/test/CodeGen/PowerPC/mma-acc-memops.ll @@ -1,19 +1,19 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ -; RUN: -disable-auto-paired-vec-st=false < %s | FileCheck %s \ +; RUN: -ppc-auto-paired-vec-st < %s | FileCheck %s \ ; RUN: --check-prefix=LE-PAIRED ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mcpu=future -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ -; RUN: -disable-auto-paired-vec-st=false < %s | FileCheck %s \ +; RUN: -ppc-auto-paired-vec-st < %s | FileCheck %s \ ; RUN: --check-prefix=LE-PAIRED-WACC ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \ -; RUN: -ppc-vsr-nums-as-vr -disable-auto-paired-vec-st=false < %s | \ +; RUN: -ppc-vsr-nums-as-vr -ppc-auto-paired-vec-st < %s | \ ; RUN: FileCheck %s --check-prefix=BE-PAIRED ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: -mcpu=future -ppc-asm-full-reg-names \ -; RUN: -ppc-vsr-nums-as-vr -disable-auto-paired-vec-st=false < %s | \ +; RUN: -ppc-vsr-nums-as-vr -ppc-auto-paired-vec-st < %s | \ ; RUN: FileCheck %s --check-prefix=BE-PAIRED-WACC ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \ ; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu < %s \ diff --git a/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll b/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll index 9db8ba1c9eb09d..ebd6cd0d208cdd 100644 --- a/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll +++ b/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll @@ -1,23 +1,23 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ -; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -disable-auto-paired-vec-st=false \ +; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-auto-paired-vec-st \ ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ -; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -disable-auto-paired-vec-st=false \ +; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-auto-paired-vec-st \ ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ -; RUN: -mcpu=pwr11 -ppc-asm-full-reg-names -disable-auto-paired-vec-st=false \ +; RUN: -mcpu=pwr11 -ppc-asm-full-reg-names -ppc-auto-paired-vec-st \ ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ -; RUN: -mcpu=pwr11 -ppc-asm-full-reg-names -disable-auto-paired-vec-st=false \ +; RUN: -mcpu=pwr11 -ppc-asm-full-reg-names -ppc-auto-paired-vec-st \ ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ -; RUN: -mcpu=future -ppc-asm-full-reg-names -disable-auto-paired-vec-st=false \ +; RUN: -mcpu=future -ppc-asm-full-reg-names -ppc-auto-paired-vec-st \ ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-LE-WACC ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ -; RUN: -mcpu=future -ppc-asm-full-reg-names -disable-auto-paired-vec-st=false \ +; RUN: -mcpu=future -ppc-asm-full-reg-names -ppc-auto-paired-vec-st \ ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE-WACC declare <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/PowerPC/optcmp.ll b/llvm/test/CodeGen/PowerPC/optcmp.ll index 831bc97cc0e9fa..2426cb301ddb2c 100644 --- a/llvm/test/CodeGen/PowerPC/optcmp.ll +++ b/llvm/test/CodeGen/PowerPC/optcmp.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -disable-ppc-cmp-opt=0 | FileCheck %s -; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -disable-ppc-cmp-opt=0 -mattr=-isel | FileCheck --check-prefix=CHECK-NO-ISEL %s +; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -ppc-cmp-opt | FileCheck %s +; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -ppc-cmp-opt -mattr=-isel | FileCheck --check-prefix=CHECK-NO-ISEL %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll b/llvm/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll index 3ec4a226e0dac9..35c41b416f211b 100644 --- a/llvm/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll +++ b/llvm/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -verify-machineinstrs -ppc-disable-perfect-shuffle=false < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -ppc-perfect-shuffle < %s | FileCheck %s ; TODO: Fix this case when disabling perfect shuffle diff --git a/llvm/test/CodeGen/PowerPC/perfect-shuffle.ll b/llvm/test/CodeGen/PowerPC/perfect-shuffle.ll index 2f7d227fa9e06b..27145f25129cbd 100644 --- a/llvm/test/CodeGen/PowerPC/perfect-shuffle.ll +++ b/llvm/test/CodeGen/PowerPC/perfect-shuffle.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple powerpc64 -mcpu=pwr10 < %s | FileCheck %s --check-prefix=BE ; RUN: llc -mtriple powerpc64le -mcpu=pwr10 < %s | FileCheck %s --check-prefix=LE -; RUN: llc -mtriple powerpc64le -mcpu=pwr10 -ppc-disable-perfect-shuffle=false < %s | FileCheck %s --check-prefix=LE -; RUN: llc -mtriple powerpc64 -mcpu=pwr10 -ppc-disable-perfect-shuffle=false < %s | FileCheck %s --check-prefix=BE-ENABLE +; RUN: llc -mtriple powerpc64le -mcpu=pwr10 -ppc-perfect-shuffle < %s | FileCheck %s --check-prefix=LE +; RUN: llc -mtriple powerpc64 -mcpu=pwr10 -ppc-perfect-shuffle < %s | FileCheck %s --check-prefix=BE-ENABLE ; TODO: Fix the worse codegen when disabling perfect shuffle diff --git a/llvm/test/CodeGen/PowerPC/pow-025-075-intrinsic-scalar-mass-afn.ll b/llvm/test/CodeGen/PowerPC/pow-025-075-intrinsic-scalar-mass-afn.ll index bc732df63ecec2..88e11ac57a2460 100644 --- a/llvm/test/CodeGen/PowerPC/pow-025-075-intrinsic-scalar-mass-afn.ll +++ b/llvm/test/CodeGen/PowerPC/pow-025-075-intrinsic-scalar-mass-afn.ll @@ -1,5 +1,5 @@ -; RUN: llc -enable-ppc-gen-scalar-mass -verify-machineinstrs -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck --check-prefix=CHECK-LNX %s -; RUN: llc -enable-ppc-gen-scalar-mass -verify-machineinstrs -O3 -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefix=CHECK-AIX %s +; RUN: llc -ppc-enable-gen-scalar-mass -verify-machineinstrs -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck --check-prefix=CHECK-LNX %s +; RUN: llc -ppc-enable-gen-scalar-mass -verify-machineinstrs -O3 -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefix=CHECK-AIX %s declare float @llvm.pow.f32 (float, float); declare double @llvm.pow.f64 (double, double); diff --git a/llvm/test/CodeGen/PowerPC/pow-025-075-intrinsic-scalar-mass-fast.ll b/llvm/test/CodeGen/PowerPC/pow-025-075-intrinsic-scalar-mass-fast.ll index ff8c7ffa272d13..3d06f89fdc7adc 100644 --- a/llvm/test/CodeGen/PowerPC/pow-025-075-intrinsic-scalar-mass-fast.ll +++ b/llvm/test/CodeGen/PowerPC/pow-025-075-intrinsic-scalar-mass-fast.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -enable-ppc-gen-scalar-mass -verify-machineinstrs -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck --check-prefix=CHECK-LNX %s -; RUN: llc -enable-ppc-gen-scalar-mass -verify-machineinstrs -O3 -mcpu=ppc -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefix=CHECK-AIX %s +; RUN: llc -ppc-enable-gen-scalar-mass -verify-machineinstrs -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck --check-prefix=CHECK-LNX %s +; RUN: llc -ppc-enable-gen-scalar-mass -verify-machineinstrs -O3 -mcpu=ppc -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefix=CHECK-AIX %s declare float @llvm.pow.f32 (float, float); declare double @llvm.pow.f64 (double, double); diff --git a/llvm/test/CodeGen/PowerPC/pow-025-075-nointrinsic-scalar-mass-fast.ll b/llvm/test/CodeGen/PowerPC/pow-025-075-nointrinsic-scalar-mass-fast.ll index 3e0cdb03d38689..80ebaee1921ba4 100644 --- a/llvm/test/CodeGen/PowerPC/pow-025-075-nointrinsic-scalar-mass-fast.ll +++ b/llvm/test/CodeGen/PowerPC/pow-025-075-nointrinsic-scalar-mass-fast.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -enable-ppc-gen-scalar-mass -verify-machineinstrs -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck --check-prefix=CHECK-LNX %s -; RUN: llc -enable-ppc-gen-scalar-mass -verify-machineinstrs -O3 -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefix=CHECK-AIX %s +; RUN: llc -ppc-enable-gen-scalar-mass -verify-machineinstrs -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck --check-prefix=CHECK-LNX %s +; RUN: llc -ppc-enable-gen-scalar-mass -verify-machineinstrs -O3 -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefix=CHECK-AIX %s declare float @powf (float, float); declare double @pow (double, double); diff --git a/llvm/test/CodeGen/PowerPC/ppc-disable-non-volatile-cr.ll b/llvm/test/CodeGen/PowerPC/ppc-disable-non-volatile-cr.ll index 81c667d5b1c596..b0d3ce3c017c0f 100644 --- a/llvm/test/CodeGen/PowerPC/ppc-disable-non-volatile-cr.ll +++ b/llvm/test/CodeGen/PowerPC/ppc-disable-non-volatile-cr.ll @@ -1,5 +1,5 @@ ; Note: Test option to disable use of non-volatile CR to avoid CR spilling in prologue. -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -ppc-disable-non-volatile-cr\ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -ppc-non-volatile-cr=false\ ; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck --check-prefix=CHECK-DISABLE %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu\ ; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck --check-prefix=CHECK-ENABLE %s diff --git a/llvm/test/CodeGen/PowerPC/ppc-passname.ll b/llvm/test/CodeGen/PowerPC/ppc-passname.ll index 8f430e4e0ba335..b17104db307781 100644 --- a/llvm/test/CodeGen/PowerPC/ppc-passname.ll +++ b/llvm/test/CodeGen/PowerPC/ppc-passname.ll @@ -95,12 +95,12 @@ ; Test pass name: ppc-branch-coalescing. -; RUN: llc -enable-ppc-branch-coalesce -mtriple=powerpc64le-unknown-unknown < %s -debug-pass=Structure -stop-before=ppc-branch-coalescing -o /dev/null 2>&1 | FileCheck %s -check-prefix=STOP-BEFORE-BRANCH-COALESCING +; RUN: llc -ppc-enable-branch-coalesce -mtriple=powerpc64le-unknown-unknown < %s -debug-pass=Structure -stop-before=ppc-branch-coalescing -o /dev/null 2>&1 | FileCheck %s -check-prefix=STOP-BEFORE-BRANCH-COALESCING ; STOP-BEFORE-BRANCH-COALESCING-NOT: -ppc-branch-coalescing ; STOP-BEFORE-BRANCH-COALESCING-NOT: "ppc-branch-coalescing" pass is not registered. ; STOP-BEFORE-BRANCH-COALESCING-NOT: Branch Coalescing -; RUN: llc -enable-ppc-branch-coalesce -mtriple=powerpc64le-unknown-unknown < %s -debug-pass=Structure -stop-after=ppc-branch-coalescing -o /dev/null 2>&1 | FileCheck %s -check-prefix=STOP-AFTER-BRANCH-COALESCING +; RUN: llc -ppc-enable-branch-coalesce -mtriple=powerpc64le-unknown-unknown < %s -debug-pass=Structure -stop-after=ppc-branch-coalescing -o /dev/null 2>&1 | FileCheck %s -check-prefix=STOP-AFTER-BRANCH-COALESCING ; STOP-AFTER-BRANCH-COALESCING: -ppc-branch-coalescing ; STOP-AFTER-BRANCH-COALESCING-NOT: "ppc-branch-coalescing" pass is not registered. ; STOP-AFTER-BRANCH-COALESCING: Branch Coalescing diff --git a/llvm/test/CodeGen/PowerPC/ppc64-get-cache-line-size.ll b/llvm/test/CodeGen/PowerPC/ppc64-get-cache-line-size.ll index 1a006000018773..217ecf0b170d65 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64-get-cache-line-size.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64-get-cache-line-size.ll @@ -1,10 +1,10 @@ -; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-ppc-prefetching=true | FileCheck %s -; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-ppc-prefetching=true -cache-line-size=64 | FileCheck %s -check-prefix=CHECK-DCBT -; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -enable-ppc-prefetching=true | FileCheck %s -; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -enable-ppc-prefetching=true -cache-line-size=64 | FileCheck %s -check-prefix=CHECK-DCBT -; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -enable-ppc-prefetching=true | FileCheck %s -; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -enable-ppc-prefetching=true -cache-line-size=64 | FileCheck %s -check-prefix=CHECK-DCBT -; RUN: llc < %s -mtriple=ppc64-- -mcpu=a2 -enable-ppc-prefetching=true | FileCheck %s -check-prefix=CHECK-DCBT +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -ppc-enable-prefetching=true | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -ppc-enable-prefetching=true -cache-line-size=64 | FileCheck %s -check-prefix=CHECK-DCBT +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ppc-enable-prefetching=true | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ppc-enable-prefetching=true -cache-line-size=64 | FileCheck %s -check-prefix=CHECK-DCBT +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -ppc-enable-prefetching=true | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -ppc-enable-prefetching=true -cache-line-size=64 | FileCheck %s -check-prefix=CHECK-DCBT +; RUN: llc < %s -mtriple=ppc64-- -mcpu=a2 -ppc-enable-prefetching=true | FileCheck %s -check-prefix=CHECK-DCBT ; Function Attrs: nounwind define signext i32 @check_cache_line() local_unnamed_addr { diff --git a/llvm/test/CodeGen/PowerPC/ppc64-sibcall-shrinkwrap.ll b/llvm/test/CodeGen/PowerPC/ppc64-sibcall-shrinkwrap.ll index 1a3aaaec037abe..4837ffee8d13ee 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64-sibcall-shrinkwrap.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64-sibcall-shrinkwrap.ll @@ -1,8 +1,8 @@ -; RUN: llc -relocation-model=static -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -disable-ppc-sco=false --enable-shrink-wrap=false | FileCheck %s -check-prefix=CHECK-SCO-ONLY -; RUN: llc -relocation-model=static -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -disable-ppc-sco=false --enable-shrink-wrap=true | FileCheck %s -check-prefix=CHECK-SCO-SR -; RUN: llc -relocation-model=static -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -disable-ppc-sco=false --enable-shrink-wrap=false | FileCheck %s -check-prefix=CHECK-SCO-ONLY -; RUN: llc -relocation-model=static -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -disable-ppc-sco=false --enable-shrink-wrap=true | FileCheck %s -check-prefix=CHECK-SCO-SR -; RUN: not --crash llc -relocation-model=pic -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff -tailcallopt -disable-ppc-sco=false --enable-shrink-wrap=true 2>&1 | FileCheck %s -check-prefix=CHECK-AIX +; RUN: llc -relocation-model=static -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -ppc-sco --enable-shrink-wrap=false | FileCheck %s -check-prefix=CHECK-SCO-ONLY +; RUN: llc -relocation-model=static -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -ppc-sco --enable-shrink-wrap=true | FileCheck %s -check-prefix=CHECK-SCO-SR +; RUN: llc -relocation-model=static -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -ppc-sco --enable-shrink-wrap=false | FileCheck %s -check-prefix=CHECK-SCO-ONLY +; RUN: llc -relocation-model=static -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -ppc-sco --enable-shrink-wrap=true | FileCheck %s -check-prefix=CHECK-SCO-SR +; RUN: not --crash llc -relocation-model=pic -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff -tailcallopt -ppc-sco --enable-shrink-wrap=true 2>&1 | FileCheck %s -check-prefix=CHECK-AIX ;; The above RUN command is expected to fail on AIX since tail calling is not implemented ATM %"class.clang::NamedDecl" = type { i32 } declare void @__assert_fail(); diff --git a/llvm/test/CodeGen/PowerPC/ppc64-sibcall.ll b/llvm/test/CodeGen/PowerPC/ppc64-sibcall.ll index 8268495e9b8b93..54ef831c5d3fc5 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64-sibcall.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64-sibcall.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -relocation-model=static -O1 -disable-ppc-sco=false -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-SCO -; RUN: llc < %s -relocation-model=static -O1 -disable-ppc-sco=false -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-SCO -; RUN: llc < %s -relocation-model=static -O1 -disable-ppc-sco=false -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-SCO -; RUN: llc < %s -relocation-model=static -O1 -disable-ppc-sco=false -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -code-model=small | FileCheck %s -check-prefix=SCM +; RUN: llc < %s -relocation-model=static -O1 -ppc-sco -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-SCO +; RUN: llc < %s -relocation-model=static -O1 -ppc-sco -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-SCO +; RUN: llc < %s -relocation-model=static -O1 -ppc-sco -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-SCO +; RUN: llc < %s -relocation-model=static -O1 -ppc-sco -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -code-model=small | FileCheck %s -check-prefix=SCM ; No combination of "powerpc64le-unknown-linux-gnu" + "CHECK-SCO", because ; only Power8 (and later) fully support LE. diff --git a/llvm/test/CodeGen/PowerPC/pr116071.ll b/llvm/test/CodeGen/PowerPC/pr116071.ll index 29f11fc1d3a630..588bca4de2976f 100644 --- a/llvm/test/CodeGen/PowerPC/pr116071.ll +++ b/llvm/test/CodeGen/PowerPC/pr116071.ll @@ -1,4 +1,4 @@ -; RUN: llc -disable-ppc-vsx-fma-mutation=false -mcpu=pwr10 -verify-machineinstrs \ +; RUN: llc -ppc-vsx-fma-mutation -mcpu=pwr10 -verify-machineinstrs \ ; RUN: -ppc-asm-full-reg-names -mtriple powerpc64-ibm-aix7.2.0.0 < %s | FileCheck %s target datalayout = "E-m:a-Fi64-i64:64-n32:64-S128-v256:256:256-v512:512:512" diff --git a/llvm/test/CodeGen/PowerPC/prefer-dqform.ll b/llvm/test/CodeGen/PowerPC/prefer-dqform.ll index 0c6a36285a933f..78c03485eb44e5 100644 --- a/llvm/test/CodeGen/PowerPC/prefer-dqform.ll +++ b/llvm/test/CodeGen/PowerPC/prefer-dqform.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -verify-machineinstrs -disable-ppc-instr-form-prep=true -mcpu=pwr9 < %s \ +; RUN: llc -verify-machineinstrs -ppc-instr-form-prep=false -mcpu=pwr9 < %s \ ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names | FileCheck %s -check-prefix=CHECK-P9 -; RUN: llc -verify-machineinstrs -disable-ppc-instr-form-prep=true -mcpu=pwr10 < %s \ +; RUN: llc -verify-machineinstrs -ppc-instr-form-prep=false -mcpu=pwr10 < %s \ ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names | FileCheck %s -check-prefix=CHECK-P10 target triple = "powerpc64le-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/PowerPC/schedule-addi-load.mir b/llvm/test/CodeGen/PowerPC/schedule-addi-load.mir index 4414dfaa43f6c8..c88a64163bbf8d 100644 --- a/llvm/test/CodeGen/PowerPC/schedule-addi-load.mir +++ b/llvm/test/CodeGen/PowerPC/schedule-addi-load.mir @@ -1,5 +1,5 @@ # RUN: llc -mcpu=pwr9 -mtriple powerpc64le-unknown-linux-gnu -start-before machine-scheduler -stop-after machine-scheduler -verify-machineinstrs %s -o - | FileCheck %s -# RUN: llc -mcpu=pwr9 -mtriple powerpc64le-unknown-linux-gnu -disable-ppc-sched-addi-load -start-before machine-scheduler -stop-after machine-scheduler \ +# RUN: llc -mcpu=pwr9 -mtriple powerpc64le-unknown-linux-gnu -ppc-sched-addi-load=false -start-before machine-scheduler -stop-after machine-scheduler \ # RUN: -verify-machineinstrs %s -o - | FileCheck --check-prefix=CHECK-DISABLE %s # RUN: llc -mcpu=pwr8 -mtriple powerpc64le-unknown-linux-gnu -start-before machine-scheduler -stop-after machine-scheduler -verify-machineinstrs %s -o - | FileCheck --check-prefix=CHECK-P8 %s diff --git a/llvm/test/CodeGen/PowerPC/spill-vec-pair.ll b/llvm/test/CodeGen/PowerPC/spill-vec-pair.ll index adca4988bc74b3..0d0a6a675cffd5 100644 --- a/llvm/test/CodeGen/PowerPC/spill-vec-pair.ll +++ b/llvm/test/CodeGen/PowerPC/spill-vec-pair.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O3 \ ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ -; RUN: -disable-auto-paired-vec-st=false < %s | FileCheck %s +; RUN: -ppc-auto-paired-vec-st < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O3 \ ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ -; RUN: -disable-auto-paired-vec-st=false < %s | FileCheck %s \ +; RUN: -ppc-auto-paired-vec-st < %s | FileCheck %s \ ; RUN: --check-prefix=CHECK-BE define dso_local void @test(ptr %vpp, ptr %vp2) local_unnamed_addr #0 { ; CHECK-LABEL: test: diff --git a/llvm/test/CodeGen/PowerPC/stwu-sched.ll b/llvm/test/CodeGen/PowerPC/stwu-sched.ll index 29a5efc0bf3f31..f29445c97d653f 100644 --- a/llvm/test/CodeGen/PowerPC/stwu-sched.ll +++ b/llvm/test/CodeGen/PowerPC/stwu-sched.ll @@ -1,8 +1,8 @@ ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s -; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -disable-ppc-ctrloops < %s -verify-machineinstrs \ +; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -ppc-enable-ctrloops=false < %s -verify-machineinstrs \ ; RUN: | FileCheck %s --check-prefix=CHECK-ITIN -; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -disable-ppc-ctrloops < %s -verify-machineinstrs \ +; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -ppc-enable-ctrloops=false < %s -verify-machineinstrs \ ; RUN: | FileCheck %s --check-prefix=CHECK-ITIN diff --git a/llvm/test/CodeGen/PowerPC/stwu8.ll b/llvm/test/CodeGen/PowerPC/stwu8.ll index a0f10af9bf5b6b..22caae0b9380e5 100644 --- a/llvm/test/CodeGen/PowerPC/stwu8.ll +++ b/llvm/test/CodeGen/PowerPC/stwu8.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -disable-ppc-unaligned < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -ppc-unaligned=false < %s | FileCheck %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/PowerPC/swaps-le-1.ll b/llvm/test/CodeGen/PowerPC/swaps-le-1.ll index 5d5445f9f473a7..55d8a952fbc337 100644 --- a/llvm/test/CodeGen/PowerPC/swaps-le-1.ll +++ b/llvm/test/CodeGen/PowerPC/swaps-le-1.ll @@ -4,7 +4,7 @@ ; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck \ ; RUN: -check-prefix=CHECK-P8 %s -; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr8 -disable-ppc-vsx-swap-removal \ +; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr8 -ppc-vsx-swap-removal=false \ ; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck \ ; RUN: -check-prefix=NOOPTSWAP-P8 %s @@ -12,7 +12,7 @@ ; RUN: -verify-machineinstrs -ppc-vsr-nums-as-vr < %s | FileCheck \ ; RUN: -check-prefix=CHECK-P9 --implicit-check-not xxswapd %s -; RUN: llc -O3 -mcpu=pwr9 -disable-ppc-vsx-swap-removal -mattr=-power9-vector \ +; RUN: llc -O3 -mcpu=pwr9 -ppc-vsx-swap-removal=false -mattr=-power9-vector \ ; RUN: -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s \ ; RUN: | FileCheck -check-prefix=NOOPTSWAP-P9 %s diff --git a/llvm/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll b/llvm/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll index 880f4baeb88546..832fde2a83778e 100644 --- a/llvm/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll +++ b/llvm/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -disable-ppc-ilp-pref | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -ppc-ilp-pref=false | FileCheck %s ; Formerly this did byte loads and word stores. @a = external global <16 x i8> @b = external global <16 x i8> diff --git a/llvm/test/CodeGen/PowerPC/vec_perf_shuffle.ll b/llvm/test/CodeGen/PowerPC/vec_perf_shuffle.ll index a1ef5c541cd4d1..1cb0f63fb24751 100644 --- a/llvm/test/CodeGen/PowerPC/vec_perf_shuffle.ll +++ b/llvm/test/CodeGen/PowerPC/vec_perf_shuffle.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 -ppc-disable-perfect-shuffle=false | not grep vperm +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 -ppc-perfect-shuffle | not grep vperm ; TODO: Fix this case when disabling perfect shuffle diff --git a/llvm/test/CodeGen/PowerPC/vsx-fma-m-early.ll b/llvm/test/CodeGen/PowerPC/vsx-fma-m-early.ll index 871aab324a99b0..2ddaab92454d37 100644 --- a/llvm/test/CodeGen/PowerPC/vsx-fma-m-early.ll +++ b/llvm/test/CodeGen/PowerPC/vsx-fma-m-early.ll @@ -1,14 +1,14 @@ ;; Tests that the ppc-vsx-fma-mutate pass with the schedule-ppc-vsx-fma-mutation-early pass does not hoist xxspltiw out of loops. -; RUN: llc -verify-machineinstrs -mcpu=pwr10 -disable-ppc-vsx-fma-mutation=false \ -; RUN: -ppc-asm-full-reg-names -schedule-ppc-vsx-fma-mutation-early \ +; RUN: llc -verify-machineinstrs -mcpu=pwr10 -ppc-vsx-fma-mutation \ +; RUN: -ppc-asm-full-reg-names -ppc-schedule-vsx-fma-mutation-early \ ; RUN: -mtriple powerpc64-ibm-aix < %s | FileCheck --check-prefixes=CHECK64,AIX64 %s -; RUN: llc -verify-machineinstrs -mcpu=pwr10 -disable-ppc-vsx-fma-mutation=false \ -; RUN: -ppc-asm-full-reg-names -schedule-ppc-vsx-fma-mutation-early \ +; RUN: llc -verify-machineinstrs -mcpu=pwr10 -ppc-vsx-fma-mutation \ +; RUN: -ppc-asm-full-reg-names -ppc-schedule-vsx-fma-mutation-early \ ; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck --check-prefixes=CHECK64,LINUX64 %s -; RUN: llc -verify-machineinstrs -mcpu=pwr10 -disable-ppc-vsx-fma-mutation=false \ -; RUN: -ppc-asm-full-reg-names -schedule-ppc-vsx-fma-mutation-early \ +; RUN: llc -verify-machineinstrs -mcpu=pwr10 -ppc-vsx-fma-mutation \ +; RUN: -ppc-asm-full-reg-names -ppc-schedule-vsx-fma-mutation-early \ ; RUN: -mtriple powerpc-ibm-aix < %s | FileCheck --check-prefix=CHECK32 %s define void @bar(ptr noalias nocapture noundef writeonly %__output_a, ptr noalias nocapture noundef readonly %var1321In_a, ptr noalias nocapture noundef readonly %n) { diff --git a/llvm/test/CodeGen/PowerPC/vsx-fma-m.ll b/llvm/test/CodeGen/PowerPC/vsx-fma-m.ll index 1feb630a1eb0e5..827b462c019339 100644 --- a/llvm/test/CodeGen/PowerPC/vsx-fma-m.ll +++ b/llvm/test/CodeGen/PowerPC/vsx-fma-m.ll @@ -2,9 +2,9 @@ ; RUN: llc -verify-machineinstrs < %s -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 | FileCheck -check-prefix=CHECK-FISL %s ; XFAIL: * -; Also run with -schedule-ppc-vsx-fma-mutation-early as a stress test for the +; Also run with -ppc-schedule-vsx-fma-mutation-early as a stress test for the ; live-interval-updating logic. -; RUN: llc -verify-machineinstrs < %s -mcpu=pwr7 -mattr=+vsx -schedule-ppc-vsx-fma-mutation-early +; RUN: llc -verify-machineinstrs < %s -mcpu=pwr7 -mattr=+vsx -ppc-schedule-vsx-fma-mutation-early target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/LoopDataPrefetch/PowerPC/basic.ll b/llvm/test/Transforms/LoopDataPrefetch/PowerPC/basic.ll index eaf0e0c3552945..6e7bc2563383c2 100644 --- a/llvm/test/Transforms/LoopDataPrefetch/PowerPC/basic.ll +++ b/llvm/test/Transforms/LoopDataPrefetch/PowerPC/basic.ll @@ -1,4 +1,4 @@ -; RUN: opt -mcpu=a2 -passes=loop-data-prefetch -mtriple=powerpc64le-unknown-linux -enable-ppc-prefetching -S < %s | FileCheck %s +; RUN: opt -mcpu=a2 -passes=loop-data-prefetch -mtriple=powerpc64le-unknown-linux -ppc-enable-prefetching -S < %s | FileCheck %s target datalayout = "E-m:e-i64:64-n32:64" define void @foo(ptr nocapture %a, ptr nocapture readonly %b) { _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
