llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-llvm-analysis Author: Fangrui Song (MaskRay) <details> <summary>Changes</summary> Rename the PowerPC CodeGen options so that they start with ppc-, and turn the -disable-* options into positive options with the default flipped. -enable-ppc-* becomes -ppc-enable-*, and -disable-ppc-ctrloops becomes -ppc-enable-ctrloops, since -ppc-gen-scalar-mass and -ppc-ctrloops are pass names. Preparatory for migrating to LibraryOptions. Aided by Opus 5.5 --- Patch is 84.46 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/230393.diff 62 Files Affected: - (modified) clang/test/CodeGen/lower-mass-end-to-end.c (+12-12) - (modified) llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp (+3-3) - (modified) llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (+3-2) - (modified) llvm/lib/Target/PowerPC/PPCISelLowering.cpp (+44-34) - (modified) llvm/lib/Target/PowerPC/PPCInstrInfo.cpp (+18-13) - (modified) llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp (+5-5) - (modified) llvm/lib/Target/PowerPC/PPCMachineScheduler.cpp (+5-5) - (modified) llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp (+5-5) - (modified) llvm/lib/Target/PowerPC/PPCTargetMachine.cpp (+32-30) - (modified) llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp (+11-9) - (modified) llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp (+5-5) - (modified) llvm/test/Analysis/CostModel/PowerPC/load_store.ll (+1-1) - (modified) llvm/test/CodeGen/PowerPC/2006-08-11-RetVector.ll (+2-2) - (modified) llvm/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll (+1-1) - (modified) llvm/test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll (+2-2) - (modified) llvm/test/CodeGen/PowerPC/addi-licm.ll (+1-1) - (modified) llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-ssp.ll (+1-1) - (modified) llvm/test/CodeGen/PowerPC/aix-ifunc-toc-restore-query-neg.ll (+1-1) - (modified) llvm/test/CodeGen/PowerPC/aix-ifunc-toc-restore-query.ll (+1-1) - (modified) llvm/test/CodeGen/PowerPC/branch_coalesce.ll (+2-2) - (modified) llvm/test/CodeGen/PowerPC/dmrp-spill.ll (+3-3) - (modified) llvm/test/CodeGen/PowerPC/fma-assoc.ll (+4-4) - (modified) llvm/test/CodeGen/PowerPC/fma-ext.ll (+2-2) - (modified) llvm/test/CodeGen/PowerPC/fma-mutate.ll (+1-1) - (modified) llvm/test/CodeGen/PowerPC/fma.ll (+4-4) - (modified) llvm/test/CodeGen/PowerPC/lbzux.ll (+1-1) - (modified) llvm/test/CodeGen/PowerPC/loop-align.ll (+6-6) - (modified) llvm/test/CodeGen/PowerPC/loop-data-prefetch-inner.ll (+1-1) - (modified) llvm/test/CodeGen/PowerPC/loop-data-prefetch.ll (+1-1) - (modified) llvm/test/CodeGen/PowerPC/lower-intrinsics-afn-mass.ll (+2-2) - (modified) llvm/test/CodeGen/PowerPC/lower-intrinsics-afn-mass_notail.ll (+2-2) - (modified) llvm/test/CodeGen/PowerPC/lower-intrinsics-fast-mass.ll (+2-2) - (modified) llvm/test/CodeGen/PowerPC/lower-intrinsics-fast-mass_notail.ll (+2-2) - (modified) llvm/test/CodeGen/PowerPC/lower-intrinsics-nofast-mass.ll (+2-2) - (modified) llvm/test/CodeGen/PowerPC/lower-scalar-mass-afn.ll (+2-2) - (modified) llvm/test/CodeGen/PowerPC/lower-scalar-mass-fast.ll (+2-2) - (modified) llvm/test/CodeGen/PowerPC/lower-scalar-mass-nofast.ll (+2-2) - (modified) llvm/test/CodeGen/PowerPC/mma-acc-memops.ll (+4-4) - (modified) llvm/test/CodeGen/PowerPC/mma-acc-spill.ll (+6-6) - (modified) llvm/test/CodeGen/PowerPC/optcmp.ll (+2-2) - (modified) llvm/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll (+1-1) - (modified) llvm/test/CodeGen/PowerPC/perfect-shuffle.ll (+2-2) - (modified) llvm/test/CodeGen/PowerPC/pow-025-075-intrinsic-scalar-mass-afn.ll (+2-2) - (modified) llvm/test/CodeGen/PowerPC/pow-025-075-intrinsic-scalar-mass-fast.ll (+2-2) - (modified) llvm/test/CodeGen/PowerPC/pow-025-075-nointrinsic-scalar-mass-fast.ll (+2-2) - (modified) llvm/test/CodeGen/PowerPC/ppc-disable-non-volatile-cr.ll (+1-1) - (modified) llvm/test/CodeGen/PowerPC/ppc-passname.ll (+2-2) - (modified) llvm/test/CodeGen/PowerPC/ppc64-get-cache-line-size.ll (+7-7) - (modified) llvm/test/CodeGen/PowerPC/ppc64-sibcall-shrinkwrap.ll (+5-5) - (modified) llvm/test/CodeGen/PowerPC/ppc64-sibcall.ll (+4-4) - (modified) llvm/test/CodeGen/PowerPC/pr116071.ll (+1-1) - (modified) llvm/test/CodeGen/PowerPC/prefer-dqform.ll (+2-2) - (modified) llvm/test/CodeGen/PowerPC/schedule-addi-load.mir (+1-1) - (modified) llvm/test/CodeGen/PowerPC/spill-vec-pair.ll (+2-2) - (modified) llvm/test/CodeGen/PowerPC/stwu-sched.ll (+2-2) - (modified) llvm/test/CodeGen/PowerPC/stwu8.ll (+1-1) - (modified) llvm/test/CodeGen/PowerPC/swaps-le-1.ll (+2-2) - (modified) llvm/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll (+1-1) - (modified) llvm/test/CodeGen/PowerPC/vec_perf_shuffle.ll (+1-1) - (modified) llvm/test/CodeGen/PowerPC/vsx-fma-m-early.ll (+6-6) - (modified) llvm/test/CodeGen/PowerPC/vsx-fma-m.ll (+2-2) - (modified) llvm/test/Transforms/LoopDataPrefetch/PowerPC/basic.ll (+1-1) ``````````diff diff --git a/clang/test/CodeGen/lower-mass-end-to-end.c b/clang/test/CodeGen/lower-mass-end-to-end.c index 41a65900d4d236..d2c82847d43845 100644 --- a/clang/test/CodeGen/lower-mass-end-to-end.c +++ b/clang/test/CodeGen/lower-mass-end-to-end.c @@ -1,18 +1,18 @@ // REQUIRES: powerpc-registered-target -// RUN: %clang -mllvm -enable-ppc-gen-scalar-mass -O3 -fapprox-func --target=powerpc64le-unknown-linux-gnu -S %s -o -| FileCheck %s -check-prefix=CHECK-MASS-AFN -// RUN: %clang -mllvm -enable-ppc-gen-scalar-mass -Ofast --target=powerpc64le-unknown-linux-gnu -S %s -o -| FileCheck %s -check-prefix=CHECK-MASS-FAST -// RUN: %clang -mllvm -enable-ppc-gen-scalar-mass -O3 -fapprox-func --target=powerpc-ibm-aix-xcoff -S %s -o -| FileCheck %s -check-prefix=CHECK-MASS-AFN -// RUN: %clang -mllvm -enable-ppc-gen-scalar-mass -Ofast --target=powerpc-ibm-aix-xcoff -S %s -o -| FileCheck %s -check-prefix=CHECK-MASS-FAST +// RUN: %clang -mllvm -ppc-enable-gen-scalar-mass -O3 -fapprox-func --target=powerpc64le-unknown-linux-gnu -S %s -o -| FileCheck %s -check-prefix=CHECK-MASS-AFN +// RUN: %clang -mllvm -ppc-enable-gen-scalar-mass -Ofast --target=powerpc64le-unknown-linux-gnu -S %s -o -| FileCheck %s -check-prefix=CHECK-MASS-FAST +// RUN: %clang -mllvm -ppc-enable-gen-scalar-mass -O3 -fapprox-func --target=powerpc-ibm-aix-xcoff -S %s -o -| FileCheck %s -check-prefix=CHECK-MASS-AFN +// RUN: %clang -mllvm -ppc-enable-gen-scalar-mass -Ofast --target=powerpc-ibm-aix-xcoff -S %s -o -| FileCheck %s -check-prefix=CHECK-MASS-FAST -// RUN: %clang -mllvm -enable-ppc-gen-scalar-mass=false -O3 -fapprox-func --target=powerpc64le-unknown-linux-gnu -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-AFN -// RUN: %clang -mllvm -enable-ppc-gen-scalar-mass=false -Ofast --target=powerpc64le-unknown-linux-gnu -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-FAST -// RUN: %clang -mllvm -enable-ppc-gen-scalar-mass=false -O3 -fapprox-func --target=powerpc-ibm-aix-xcoff -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-AFN -// RUN: %clang -mllvm -enable-ppc-gen-scalar-mass=false -Ofast --target=powerpc-ibm-aix-xcoff -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-FAST +// RUN: %clang -mllvm -ppc-enable-gen-scalar-mass=false -O3 -fapprox-func --target=powerpc64le-unknown-linux-gnu -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-AFN +// RUN: %clang -mllvm -ppc-enable-gen-scalar-mass=false -Ofast --target=powerpc64le-unknown-linux-gnu -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-FAST +// RUN: %clang -mllvm -ppc-enable-gen-scalar-mass=false -O3 -fapprox-func --target=powerpc-ibm-aix-xcoff -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-AFN +// RUN: %clang -mllvm -ppc-enable-gen-scalar-mass=false -Ofast --target=powerpc-ibm-aix-xcoff -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-FAST -// RUN: %clang -mllvm -enable-ppc-gen-scalar-mass -O3 -fno-approx-func --target=powerpc64le-unknown-linux-gnu -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-AFN -// RUN: %clang -mllvm -enable-ppc-gen-scalar-mass -fno-fast-math --target=powerpc64le-unknown-linux-gnu -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-FAST -// RUN: %clang -mllvm -enable-ppc-gen-scalar-mass -O3 -fno-approx-func --target=powerpc-ibm-aix-xcoff -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-AFN -// RUN: %clang -mllvm -enable-ppc-gen-scalar-mass -fno-fast-math --target=powerpc-ibm-aix-xcoff -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-FAST +// RUN: %clang -mllvm -ppc-enable-gen-scalar-mass -O3 -fno-approx-func --target=powerpc64le-unknown-linux-gnu -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-AFN +// RUN: %clang -mllvm -ppc-enable-gen-scalar-mass -fno-fast-math --target=powerpc64le-unknown-linux-gnu -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-FAST +// RUN: %clang -mllvm -ppc-enable-gen-scalar-mass -O3 -fno-approx-func --target=powerpc-ibm-aix-xcoff -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-AFN +// RUN: %clang -mllvm -ppc-enable-gen-scalar-mass -fno-fast-math --target=powerpc-ibm-aix-xcoff -S %s -o -| FileCheck %s -check-prefix=CHECK-NO-MASS-FAST extern double sin(double a); extern double cos(double a); diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp index 0d3275b4b56c5b..e2e3d0f70d0e19 100644 --- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -99,11 +99,11 @@ STATISTIC(NumTOCBlockAddress, "Number of Block Address TOC Entries."); STATISTIC(NumTOCEHBlock, "Number of EH Block TOC Entries."); static cl::opt<bool> EnableSSPCanaryBitInTB( - "aix-ssp-tb-bit", cl::init(false), + "ppc-aix-ssp-tb-bit", cl::init(false), cl::desc("Enable Passing SSP Canary info in Trackback on AIX"), cl::Hidden); static cl::opt<bool> IFuncLocalIfProven( - "ifunc-local-if-proven", cl::init(false), + "ppc-ifunc-local-if-proven", cl::init(false), cl::desc("During ifunc lowering, the compiler assumes the resolver returns " "dso-local functions and bails out if non-local functions are " "detected; this flag flips the assumption: resolver returns " @@ -112,7 +112,7 @@ static cl::opt<bool> IFuncLocalIfProven( cl::Hidden); // this flag is used for testing only as it might generate bad code. -static cl::opt<bool> IFuncWarnInsteadOfError("test-ifunc-warn-noerror", +static cl::opt<bool> IFuncWarnInsteadOfError("ppc-test-ifunc-warn-noerror", cl::init(false), cl::ReallyHidden); // Specialize DenseMapInfo to allow diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index ec276e9880f109..43258d8ff0b879 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -88,8 +88,9 @@ STATISTIC(NumP9Setb, "Number of compares lowered to setb."); // FIXME: Remove this once the bug has been fixed! -cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug", -cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden); +cl::opt<bool> ANDIGlueBug("ppc-expose-andi-glue-bug", + cl::desc("expose the ANDI glue bug on PPC"), + cl::Hidden); static cl::opt<bool> UseBitPermRewriter("ppc-use-bit-perm-rewriter", cl::init(true), diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 05f42551b690f1..25991b74cb599b 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -104,38 +104,45 @@ using namespace llvm; extern cl::opt<bool> EnablePPCGenScalarMASSEntries; -static cl::opt<bool> DisableP10StoreForward( - "disable-p10-store-forward", - cl::desc("disable P10 store forward-friendly conversion"), cl::Hidden, - cl::init(false)); +static cl::opt<bool> EnableP10StoreForward( + "ppc-p10-store-forward", + cl::desc("enable P10 store forward-friendly conversion"), cl::init(true), + cl::Hidden); -static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc", -cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden); +static cl::opt<bool> EnablePPCPreinc( + "ppc-preinc", cl::desc("enable preincrement load/store generation on PPC"), + cl::init(true), cl::Hidden); -static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref", -cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden); +static cl::opt<bool> EnableILPPref( + "ppc-ilp-pref", + cl::desc("enable setting the node scheduling preference to ILP on PPC"), + cl::init(true), cl::Hidden); -static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned", -cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden); +static cl::opt<bool> EnablePPCUnaligned( + "ppc-unaligned", cl::desc("enable unaligned load/store generation on PPC"), + cl::init(true), cl::Hidden); -static cl::opt<bool> DisableSCO("disable-ppc-sco", -cl::desc("disable sibling call optimization on ppc"), cl::Hidden); +static cl::opt<bool> + EnableSCO("ppc-sco", cl::desc("enable sibling call optimization on ppc"), + cl::init(true), cl::Hidden); -static cl::opt<bool> DisableInnermostLoopAlign32("disable-ppc-innermost-loop-align32", -cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden); +static cl::opt<bool> EnableInnermostLoopAlign32( + "ppc-innermost-loop-align32", + cl::desc("always align innermost loop to 32 bytes on ppc"), cl::init(true), + cl::Hidden); static cl::opt<bool> UseAbsoluteJumpTables("ppc-use-absolute-jumptables", cl::desc("use absolute jump tables on ppc"), cl::Hidden); static cl::opt<bool> - DisablePerfectShuffle("ppc-disable-perfect-shuffle", - cl::desc("disable vector permute decomposition"), - cl::init(true), cl::Hidden); + EnablePerfectShuffle("ppc-perfect-shuffle", + cl::desc("enable vector permute decomposition"), + cl::init(false), cl::Hidden); -cl::opt<bool> DisableAutoPairedVecSt( - "disable-auto-paired-vec-st", - cl::desc("disable automatically generated 32byte paired vector stores"), - cl::init(true), cl::Hidden); +cl::opt<bool> EnableAutoPairedVecSt( + "ppc-auto-paired-vec-st", + cl::desc("enable automatically generated 32byte paired vector stores"), + cl::init(false), cl::Hidden); static cl::opt<unsigned> PPCMinimumJumpTableEntries( "ppc-min-jump-table-entries", cl::init(64), cl::Hidden, @@ -1042,7 +1049,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, // LE is P8+/64-bit so direct moves are supported and these operations // are legal. The custom transformation requires 64-bit since we need a // pair of stores that will cover a 128-bit load for P10. - if (!DisableP10StoreForward && isPPC64 && !Subtarget.isLittleEndian()) { + if (EnableP10StoreForward && isPPC64 && !Subtarget.isLittleEndian()) { setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Custom); setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); @@ -1560,8 +1567,8 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, // Enable generation of STXVP instructions by default for mcpu=future. if (CPUDirective == PPC::DIR_PWR_FUTURE && - DisableAutoPairedVecSt.getNumOccurrences() == 0) - DisableAutoPairedVecSt = false; + EnableAutoPairedVecSt.getNumOccurrences() == 0) + EnableAutoPairedVecSt = true; IsStrictFPEnabled = true; @@ -2937,7 +2944,8 @@ bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const { - if (DisablePPCPreinc) return false; + if (!EnablePPCPreinc) + return false; bool isLoad = true; SDValue Ptr; @@ -5018,7 +5026,8 @@ bool PPCTargetLowering::IsEligibleForTailCallOptimization_64SVR4( bool isCalleeExternalSymbol) const { bool TailCallOpt = getTargetMachine().Options.GuaranteedTailCallOpt; - if (DisableSCO && !TailCallOpt) return false; + if (!EnableSCO && !TailCallOpt) + return false; // Variadic argument functions are not supported. if (isVarArg) return false; @@ -5077,7 +5086,8 @@ bool PPCTargetLowering::IsEligibleForTailCallOptimization_64SVR4( if (CalleeCC == CallingConv::Fast && TailCallOpt) return true; - if (DisableSCO) return false; + if (!EnableSCO) + return false; // If callee use the same argument list that caller is using, then we can // apply SCO on this case. If it is not, then we need to check if callee needs @@ -10650,7 +10660,7 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, // perfect shuffle table to emit an optimal matching sequence. ArrayRef<int> PermMask = SVOp->getMask(); - if (!DisablePerfectShuffle && !isLittleEndian) { + if (EnablePerfectShuffle && !isLittleEndian) { unsigned PFIndexes[4]; bool isFourElementShuffle = true; for (unsigned i = 0; i != 4 && isFourElementShuffle; @@ -12103,7 +12113,7 @@ SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, // to avoid load hit store on P10 when running binaries compiled for older // processors by generating two mergeable scalar stores to forward with the // vector load. - if (!DisableP10StoreForward && Subtarget.isPPC64() && + if (EnableP10StoreForward && Subtarget.isPPC64() && !Subtarget.isLittleEndian() && ValVT.isInteger() && ValVT.getSizeInBits() <= 64) { Val = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, Val); @@ -12473,7 +12483,7 @@ SDValue PPCTargetLowering::LowerVectorStore(SDValue Op, // For v256i1 on ISA Future, let the store go through to instruction selection // where it will be matched to stxvp/pstxvp by the instruction patterns. if (StoreVT == MVT::v256i1 && Subtarget.isISAFuture() && - !DisableAutoPairedVecSt) + EnableAutoPairedVecSt) return Op; // For other cases, create 2 or 4 v16i8 stores to store the pair or @@ -18874,7 +18884,7 @@ Align PPCTargetLowering::getPrefLoopAlignment( if (!ML) break; - if (!DisableInnermostLoopAlign32) { + if (EnableInnermostLoopAlign32) { // If the nested loop is an innermost loop, prefer to a 32-byte alignment, // so that we can decrease cache misses and branch-prediction misses. // Actual alignment of the loop will depend on the hotness check and other @@ -19646,7 +19656,7 @@ bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const { bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT, unsigned, Align, MachineMemOperand::Flags, unsigned *Fast) const { - if (DisablePPCUnaligned) + if (!EnablePPCUnaligned) return false; // PowerPC supports unaligned memory access for simple non-vector types. @@ -19817,7 +19827,7 @@ PPCTargetLowering::shouldExpandBuildVectorWithShuffles( } Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const { - if (DisableILPPref || Subtarget.enableMachineScheduler()) + if (!EnableILPPref || Subtarget.enableMachineScheduler()) return TargetLowering::getSchedulingPreference(N); return Sched::ILP; @@ -20489,7 +20499,7 @@ bool PPCTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const { // If sibling calls have been disabled and tail-calls aren't guaranteed // there is no reason to duplicate. auto &TM = getTargetMachine(); - if (!TM.Options.GuaranteedTailCallOpt && DisableSCO) + if (!TM.Options.GuaranteedTailCallOpt && !EnableSCO) return false; // Can't tail call a function called indirectly, or if it has variadic args. diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index 776d7db1abe292..b7b94800ce6e80 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -62,16 +62,21 @@ STATISTIC(MissedConvertibleImmediateInstrs, STATISTIC(NumRcRotatesConvertedToRcAnd, "Number of record-form rotates converted to record-form andi"); -static cl:: -opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden, - cl::desc("Disable analysis for CTR loops")); +static cl::opt<bool> + EnableCTRLoopAnal("ppc-ctrloop-analysis", + cl::desc("Enable analysis for CTR loops"), cl::init(true), + cl::Hidden); -static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt", -cl::desc("Disable compare instruction optimization"), cl::Hidden); +static cl::opt<bool> + EnableCmpOpt("ppc-cmp-opt", + cl::desc("Enable compare instruction optimization"), + cl::init(true), cl::Hidden); -static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy", -cl::desc("Causes the backend to crash instead of generating a nop VSX copy"), -cl::Hidden); +static cl::opt<bool> VSXSelfCopyCrash( + "ppc-crash-on-vsx-self-copy", + cl::desc( + "Causes the backend to crash instead of generating a nop VSX copy"), + cl::Hidden); static cl::opt<bool> UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden, @@ -1324,7 +1329,7 @@ bool PPCInstrInfo::analyzeBranch(MachineBasicBlock &MBB, LastInst.getOpcode() == PPC::BDNZ) { if (!LastInst.getOperand(0).isMBB()) return true; - if (DisableCTRLoopAnal) + if (!EnableCTRLoopAnal) return true; TBB = LastInst.getOperand(0).getMBB(); Cond.push_back(MachineOperand::CreateImm(1)); @@ -1335,7 +1340,7 @@ bool PPCInstrInfo::analyzeBranch(MachineBasicBlock &MBB, LastInst.getOpcode() == PPC::BDZ) { if (!LastInst.getOperand(0).isMBB()) return true; - if (DisableCTRLoopAnal) + if (!EnableCTRLoopAnal) return true; TBB = LastInst.getOperand(0).getMBB(); Cond.push_back(MachineOperand::CreateImm(0)); @@ -1392,7 +1397,7 @@ bool PPCInstrInfo::analyzeBranch(MachineBasicBlock &MBB, if (!SecondLastInst.getOperand(0).isMBB() || !LastInst.getOperand(0).isMBB()) return true; - if (DisableCTRLoopAnal) + if (!EnableCTRLoopAnal) return true; TBB = SecondLastInst.getOperand(0).getMBB(); Cond.push_back(MachineOperand::CreateImm(1)); @@ -1406,7 +1411,7 @@ bool PPCInstrInfo::analyzeBranch(MachineBasicBlock &MBB, if (!SecondLastInst.getOperand(0).isMBB() || !LastInst.getOperand(0).isMBB()) return true; - if (DisableCTRLoopAnal) + if (!EnableCTRLoopAnal) return true; TBB = SecondLastInst.getOperand(0).getMBB(); Cond.push_back(MachineOperand::CreateImm(0)); @@ -2434,7 +2439,7 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const { - if (DisableCmpOpt) + if (!EnableCmpOpt) return false; int OpC = CmpInstr.getOpcode(); diff --git a/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp b/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp index 43c667e7f04aae..f01e9f84e6d778 100644 --- a/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp @@ -14,15 +14,15 @@ #include "llvm/Support/CommandLine.h" using namespace llvm; -static cl::opt<bool> PPCDisableNonVolatileCR( - "ppc-disable-non-volatile-cr", - cl::desc("Disable the use of non-volatile CR register fields"), - cl::init(false), cl::Hidden); +static cl::opt<bool> PPCEnableNonVolatileCR( + "ppc-non-volatile-cr", + cl::desc("Enable the use of non-volatile CR register fields"), + cl::init(true), cl::Hidden); void PPCFunctionInfo::anchor() {} PPCFunctionInfo::PPCFunctionInfo(const Function &F, const TargetSubtargetInfo *STI) - : DisableNonVolatileCR(PPCDisableNonVolatileCR) {} + : DisableNonVolatileCR(!PPCEnableNonVolatileCR) {} MachineFunctionInfo * PPCFunctionInfo::clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, diff --git a/llvm/lib/Target/PowerPC/PPCMachineScheduler.cpp b/llvm/lib/Target/PowerPC/PPCMachineScheduler.cpp index b7e2263424863c..cd6f2ad7fe5f44 100644 --- a/llvm/lib/Target/PowerPC/PPCMachineScheduler.cpp +++ b/llvm/lib/Target/PowerPC/PPCMachineScheduler.cpp @@ -11,10 +11,10 @@ using namespace llvm; -static cl::opt<bool> -DisableAddiLoadHeuristic("disable-ppc-sched-addi-load", - cl::desc("Disable scheduling addi instruction before" - "load for ppc"), cl::Hidden); +static cl::opt<bool> EnableAddiLoadHeuristic( + "ppc-sched-addi-load", + cl::desc("Enable scheduling addi instruction before load for ppc"), + cl::init(true), cl::Hidden); static cl::opt<bool> EnableAddiHeuristic("ppc-postra-bias-addi", cl::desc("Enable scheduling addi instruction as early" @@ -29,7 +29,7 @@ static bool isADDIInstr(const GenericSchedule... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/230393 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
