The lab will be set up in a fashion where less emphasis will be placed on
configs (contrary to CCIE r/s) and more so on your design. The proctor will
test your design with a software program able to simulate various
applications, and a large volume of devices. So in essence, you can throw
together your design, and it will be stress tested. I don't know too many
details as the test is still being developed, but that is the basic jist of
it.
I know a lot more platforms are fair game on the lab (such as AS5300, etc).
Chris
>From: [EMAIL PROTECTED]
>Reply-To: [EMAIL PROTECTED]
>To: [EMAIL PROTECTED]
>Subject: CCIE Design
>Date: Wed, 5 Jul 2000 15:48:20 +0300
>
>Hi.
>Does anybody know format of CCIE Design Lab Exam?
>thanks.
>
> > Ali Burçin KOZAK
> > [EMAIL PROTECTED]
> > Network |
> > ------------------G R U B U------------------
> * 90-216-556 13 53
> > Fax 90-216-556 11 88
> >
>
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