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commit 8c235085105394ce9dce6f22536b114786d5f3d6 Author: raiden00pl <[email protected]> AuthorDate: Sun Aug 16 11:13:37 2026 +0200 arch/arm/stm32u5: use common Kconfig symbols CONFIG_STM32U5_I2C3EN, SDMMC1EN, SDMMC2EN, the STM32U5xxXX family names and STM32U5A5ZJT are not defined by any Kconfig, so the RCC clock enables and the STM32U5A5ZJT block in chip.h are dead code. Use the common CONFIG_STM32_* symbols and CONFIG_ARCH_CHIP_STM32U5A5ZJT. Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- arch/arm/include/stm32u5/chip.h | 8 +++--- arch/arm/include/stm32u5/irq.h | 8 +++--- arch/arm/include/stm32u5/stm32u5xx_irq.h | 16 ++++++------ arch/arm/src/stm32u5/hardware/stm32_flash.h | 4 +-- arch/arm/src/stm32u5/hardware/stm32_memorymap.h | 8 +++--- arch/arm/src/stm32u5/hardware/stm32_spi.h | 8 +++--- arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h | 10 ++++---- arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h | 10 ++++---- arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h | 10 ++++---- arch/arm/src/stm32u5/stm32_allocateheap.c | 14 +++++------ arch/arm/src/stm32u5/stm32_tim.c | 32 ++++++++++++------------ arch/arm/src/stm32u5/stm32u5xx_rcc.c | 10 ++++---- 12 files changed, 69 insertions(+), 69 deletions(-) diff --git a/arch/arm/include/stm32u5/chip.h b/arch/arm/include/stm32u5/chip.h index e0590348d6f..c984c6f80c8 100644 --- a/arch/arm/include/stm32u5/chip.h +++ b/arch/arm/include/stm32u5/chip.h @@ -33,14 +33,14 @@ * Pre-processor Prototypes ****************************************************************************/ -#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) +#if defined(CONFIG_STM32_STM32U535XX) || defined(CONFIG_STM32_STM32U545XX) # define STM32_SRAM1_SIZE (0x00030000) /* 192Kb SRAM1 */ # define STM32_SRAM2_SIZE (0x00010000) /* 64kB SRAM2 */ -#elif defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) +#elif defined(CONFIG_STM32_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) # define STM32_SRAM1_SIZE (0x00030000) /* 192Kb SRAM1 */ # define STM32_SRAM2_SIZE (0x00010000) /* 64kB SRAM2 */ # define STM32_SRAM3_SIZE (0x00080000) /* 512kB SRAM3 */ -#elif defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#elif defined(CONFIG_STM32_STM32U59XX) || defined(CONFIG_STM32_STM32U59AXX) || defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32_STM32U5A9XX) # define STM32_SRAM1_SIZE (0x000C0000) /* 768Kb SRAM1 */ # define STM32_SRAM2_SIZE (0x00010000) /* 64kB SRAM2 */ # define STM32_SRAM3_SIZE (0x000d0000) /* 832kB SRAM3 */ @@ -80,7 +80,7 @@ # define STM32_NOPAMP 2 /* Operational Amplifiers */ #endif /* CONFIG_STM32_STM32U585XX */ -#if defined(CONFIG_STM32U5_STM32U5A5ZJT) +#if defined(CONFIG_ARCH_CHIP_STM32U5A5ZJT) # define STM32_NUSBOTGHS 1 /* USB OTG HS */ #endif diff --git a/arch/arm/include/stm32u5/irq.h b/arch/arm/include/stm32u5/irq.h index 9810b119e02..1dd4a1abe7c 100644 --- a/arch/arm/include/stm32u5/irq.h +++ b/arch/arm/include/stm32u5/irq.h @@ -33,10 +33,10 @@ #include <nuttx/config.h> -#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ - defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#if defined(CONFIG_STM32_STM32U535XX) || defined(CONFIG_STM32_STM32U545XX) || \ + defined(CONFIG_STM32_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ + defined(CONFIG_STM32_STM32U59XX) || defined(CONFIG_STM32_STM32U59AXX) || \ + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32_STM32U5A9XX) # include <arch/stm32u5/stm32u5xx_irq.h> #else # error "Unsupported STM32U5 chip" diff --git a/arch/arm/include/stm32u5/stm32u5xx_irq.h b/arch/arm/include/stm32u5/stm32u5xx_irq.h index e29a074fde6..bb629ca1eeb 100644 --- a/arch/arm/include/stm32u5/stm32u5xx_irq.h +++ b/arch/arm/include/stm32u5/stm32u5xx_irq.h @@ -130,11 +130,11 @@ #define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 70) /* 70: TIM16 global interrupt */ #define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 71) /* 71: TIM17 global interrupt */ #define STM32_IRQ_COMP (STM32_IRQ_FIRST + 72) /* 72: COMP1/COMP2 interrupts */ -#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) +#if defined(CONFIG_STM32_STM32U535XX) || defined(CONFIG_STM32_STM32U545XX) || \ + defined(CONFIG_STM32_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) # define STM32_IRQ_OTG_FS (STM32_IRQ_FIRST + 73) /* 73: USB OTG FS global interrupt */ -#elif defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#elif defined(CONFIG_STM32_STM32U59XX) || defined(CONFIG_STM32_STM32U59AXX) || \ + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32_STM32U5A9XX) # define STM32_IRQ_OTG_HS (STM32_IRQ_FIRST + 73) /* 73: USB OTG HS global interrupt */ #else # error "Unsupported STM32U5 chip" @@ -191,10 +191,10 @@ #define STM32_IRQ_CORDIC (STM32_IRQ_FIRST + 123) /* 123: CORDIC interrupt */ #define STM32_IRQ_FMAC (STM32_IRQ_FIRST + 124) /* 124: FMAC interrupt */ -#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ - defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#if defined(CONFIG_STM32_STM32U535XX) || defined(CONFIG_STM32_STM32U545XX) || \ + defined(CONFIG_STM32_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ + defined(CONFIG_STM32_STM32U59XX) || defined(CONFIG_STM32_STM32U59AXX) || \ + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32_STM32U5A9XX) # define STM32_IRQ_NEXTINTS 125 #else # error "Unsupported STM32U5 chip" diff --git a/arch/arm/src/stm32u5/hardware/stm32_flash.h b/arch/arm/src/stm32u5/hardware/stm32_flash.h index ea9a8b6990f..9377ee243f2 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_flash.h +++ b/arch/arm/src/stm32u5/hardware/stm32_flash.h @@ -36,9 +36,9 @@ /* Flash size is known from the chip selection: * * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32U5_FLASH_CONFIG_x selects the default FLASH size based on + * CONFIG_STM32_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. This value can be overridden with - * CONFIG_STM32U5_FLASH_OVERRIDE_x + * CONFIG_STM32_FLASH_OVERRIDE_x * * Parts STM32U585 and STM32U575 have 2048Kb of FLASH */ diff --git a/arch/arm/src/stm32u5/hardware/stm32_memorymap.h b/arch/arm/src/stm32u5/hardware/stm32_memorymap.h index 8655250979f..fde84791f9b 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_memorymap.h +++ b/arch/arm/src/stm32u5/hardware/stm32_memorymap.h @@ -45,13 +45,13 @@ /* Code Base Addresses ******************************************************/ -#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) +#if defined(CONFIG_STM32_STM32U535XX) || defined(CONFIG_STM32_STM32U545XX) # define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ # define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x081fffff: FLASH memory */ # define STM32_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192k SRAM1 */ # define STM32_SRAM2_BASE 0x20030000 /* 0x20030000-0x2003ffff: 64k SRAM2 */ -#elif defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) +#elif defined(CONFIG_STM32_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) # define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ # define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x081fffff: FLASH memory */ @@ -59,8 +59,8 @@ # define STM32_SRAM2_BASE 0x20030000 /* 0x20030000-0x2003ffff: 64k SRAM2 */ # define STM32_SRAM3_BASE 0x20040000 /* 0x20040000-0x200bffff: 512k SRAM3 */ -#elif defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#elif defined(CONFIG_STM32_STM32U59XX) || defined(CONFIG_STM32_STM32U59AXX) || \ + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32_STM32U5A9XX) # define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ # define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x081fffff: FLASH memory */ diff --git a/arch/arm/src/stm32u5/hardware/stm32_spi.h b/arch/arm/src/stm32u5/hardware/stm32_spi.h index e230964aff0..79ff49f92d1 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_spi.h +++ b/arch/arm/src/stm32u5/hardware/stm32_spi.h @@ -30,10 +30,10 @@ #include <nuttx/config.h> #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ - defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#if defined(CONFIG_STM32_STM32U535XX) || defined(CONFIG_STM32_STM32U545XX) || \ + defined(CONFIG_STM32_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ + defined(CONFIG_STM32_STM32U59XX) || defined(CONFIG_STM32_STM32U59AXX) || \ + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32_STM32U5A9XX) # include "hardware/stm32u5xx_spi.h" #else # error "Unsupported STM32U5 chip" diff --git a/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h b/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h index 3e5ca6181a3..f78e13bfccd 100644 --- a/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h +++ b/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h @@ -29,10 +29,10 @@ #include <nuttx/config.h> -#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ - defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#if defined(CONFIG_STM32_STM32U535XX) || defined(CONFIG_STM32_STM32U545XX) || \ + defined(CONFIG_STM32_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ + defined(CONFIG_STM32_STM32U59XX) || defined(CONFIG_STM32_STM32U59AXX) || \ + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32_STM32U5A9XX) /**************************************************************************** * Pre-processor Definitions @@ -1254,5 +1254,5 @@ # define RCC_CCIPR2_OSPISEL_MSI (1 << RCC_CCIPR2_OSPISEL_SHIFT) # define RCC_CCIPR2_OSPISEL_PLL48M1CLK (2 << RCC_CCIPR2_OSPISEL_SHIFT) -#endif /* CONFIG_STM32U5_STM32U5XX */ +#endif /* CONFIG_STM32_STM32U5XX */ #endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XX_RCC_H */ diff --git a/arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h b/arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h index 241b83dadc9..e79a2bf2daa 100644 --- a/arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h +++ b/arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h @@ -29,10 +29,10 @@ #include <nuttx/config.h> -#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ - defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#if defined(CONFIG_STM32_STM32U535XX) || defined(CONFIG_STM32_STM32U545XX) || \ + defined(CONFIG_STM32_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ + defined(CONFIG_STM32_STM32U59XX) || defined(CONFIG_STM32_STM32U59AXX) || \ + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32_STM32U5A9XX) /**************************************************************************** * Pre-processor Definitions @@ -408,5 +408,5 @@ #define SPI_UDRDR_UDRDR_MASK (0xffff << SPI_UDRDR_UDRDR_SHIFT) /* Bits 16-31: read zero */ -#endif /* CONFIG_STM32U5_STM32U5XX ... */ +#endif /* CONFIG_STM32_STM32U5XX ... */ #endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XX_SPI_H */ diff --git a/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h b/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h index a531723ba39..3cb7aec33dc 100644 --- a/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h +++ b/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h @@ -30,10 +30,10 @@ #include <nuttx/config.h> #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ - defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#if defined(CONFIG_STM32_STM32U535XX) || defined(CONFIG_STM32_STM32U545XX) || \ + defined(CONFIG_STM32_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ + defined(CONFIG_STM32_STM32U59XX) || defined(CONFIG_STM32_STM32U59AXX) || \ + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32_STM32U5A9XX) /**************************************************************************** * Pre-processor Definitions @@ -136,5 +136,5 @@ #define SYSCFG_RSSCMDR_SHIFT 0 #define SYSCFG_RSSCMDR_MASK (0xFFFF << SYSCFG_RSSCMDR_SHIFT) -#endif /* CONFIG_STM32U5_STM32U5XX ... */ +#endif /* CONFIG_STM32_STM32U5XX ... */ #endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32u5/stm32_allocateheap.c b/arch/arm/src/stm32u5/stm32_allocateheap.c index 3e971fc2bc0..96785ea2182 100644 --- a/arch/arm/src/stm32u5/stm32_allocateheap.c +++ b/arch/arm/src/stm32u5/stm32_allocateheap.c @@ -61,7 +61,7 @@ * be present in the NuttX configuration file: * * CONFIG_STM32_FSMC=y : Enables the FSMC - * CONFIG_STM32U5_FSMC_SRAM=y : Indicates that SRAM is available via the + * CONFIG_STM32_FSMC_SRAM=y : Indicates that SRAM is available via the * FSMC (as opposed to an LCD or FLASH). * CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC * address space @@ -72,7 +72,7 @@ */ #ifndef CONFIG_STM32_FSMC -# undef CONFIG_STM32U5_FSMC_SRAM +# undef CONFIG_STM32_FSMC_SRAM #endif /* STM32U5[7,8]6xx have 128 Kib in two banks, both accessible to DMA: @@ -124,14 +124,14 @@ #if CONFIG_MM_REGIONS < defined(CONFIG_STM32_SRAM2_HEAP) + \ defined(CONFIG_STM32_SRAM3_HEAP) + \ defined(CONFIG_STM32_SRAM5_HEAP) + \ - defined(CONFIG_STM32U5_FSMC_SRAM_HEAP) + 1 + defined(CONFIG_STM32_FSMC_SRAM_HEAP) + 1 # error "You need more memory manager regions to support selected heap components" #endif #if CONFIG_MM_REGIONS > defined(CONFIG_STM32_SRAM2_HEAP) + \ defined(CONFIG_STM32_SRAM3_HEAP) + \ defined(CONFIG_STM32_SRAM5_HEAP) + \ - defined(CONFIG_STM32U5_FSMC_SRAM_HEAP) + 1 + defined(CONFIG_STM32_FSMC_SRAM_HEAP) + 1 # warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are" #endif @@ -140,10 +140,10 @@ * configuration (as CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE). */ -#ifdef CONFIG_STM32U5_FSMC_SRAM +#ifdef CONFIG_STM32_FSMC_SRAM # if !defined(CONFIG_HEAP2_BASE) || !defined(CONFIG_HEAP2_SIZE) # error "CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE must be provided" -# undef CONFIG_STM32U5_FSMC_SRAM +# undef CONFIG_STM32_FSMC_SRAM # endif #endif @@ -379,7 +379,7 @@ void arm_addregion(void) #endif /* SRAM5 */ -#ifdef CONFIG_STM32U5_FSMC_SRAM_HEAP +#ifdef CONFIG_STM32_FSMC_SRAM_HEAP # if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) /* Allow user-mode access to the FSMC SRAM user heap memory */ diff --git a/arch/arm/src/stm32u5/stm32_tim.c b/arch/arm/src/stm32u5/stm32_tim.c index 3f1b5472cd0..487e703c8b4 100644 --- a/arch/arm/src/stm32u5/stm32_tim.c +++ b/arch/arm/src/stm32u5/stm32_tim.c @@ -54,20 +54,20 @@ * include: * * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32U5_TIMn is defined then the CONFIG_STM32U5_TIMn_PWM may also + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may also * be defined to indicate that the timer is intended to be used for pulsed * output modulation. * - * - To control periodic ADC input sampling. If CONFIG_STM32U5_TIMn is - * defined then CONFIG_STM32U5_TIMn_ADC may also be defined to indicate + * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is + * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate * that timer "n" is intended to be used for that purpose. * - * - To control periodic DAC outputs. If CONFIG_STM32U5_TIMn is defined then - * CONFIG_STM32U5_TIMn_DAC may also be defined to indicate that timer "n" + * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_DAC may also be defined to indicate that timer "n" * is intended to be used for that purpose. * - * - To use a Quadrature Encoder. If CONFIG_STM32U5_TIMn is defined then - * CONFIG_STM32U5_TIMn_QE may also be defined to indicate that timer "n" + * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" * is intended to be used for that purpose. * * In any of these cases, the timer will not be used by this timer module. @@ -98,13 +98,13 @@ # undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32U5_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ - defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32U5_TIM6_QE) +#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) # undef CONFIG_STM32_TIM6 #endif -#if defined(CONFIG_STM32U5_TIM7_PWM) || defined (CONFIG_STM32U5_TIM7_ADC) || \ - defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32U5_TIM7_QE) +#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \ + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) # undef CONFIG_STM32_TIM7 #endif @@ -114,17 +114,17 @@ #endif #if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ - defined(CONFIG_STM32U5_TIM15_DAC) || defined(CONFIG_STM32U5_TIM15_QE) + defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) # undef CONFIG_STM32_TIM15 #endif -#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32U5_TIM16_ADC) || \ - defined(CONFIG_STM32U5_TIM16_DAC) || defined(CONFIG_STM32U5_TIM16_QE) +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \ + defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) # undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32U5_TIM17_ADC) || \ - defined(CONFIG_STM32U5_TIM17_DAC) || defined(CONFIG_STM32U5_TIM17_QE) +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \ + defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) # undef CONFIG_STM32_TIM17 #endif diff --git a/arch/arm/src/stm32u5/stm32u5xx_rcc.c b/arch/arm/src/stm32u5/stm32u5xx_rcc.c index 3a044f6a8ee..d696cd02a5d 100644 --- a/arch/arm/src/stm32u5/stm32u5xx_rcc.c +++ b/arch/arm/src/stm32u5/stm32u5xx_rcc.c @@ -92,7 +92,7 @@ static inline void rcc_enableahb1(void) regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32U5_GPDMA1 +#ifdef CONFIG_STM32_GPDMA1 regval |= RCC_AHB1ENR_GPDMA1EN; #endif @@ -242,11 +242,11 @@ static inline void rcc_enableahb2(void) regval |= RCC_AHB2ENR1_OTFDEC2; #endif -#ifdef CONFIG_STM32U5_SDMMC1EN +#ifdef CONFIG_STM32_SDMMC1 regval |= RCC_AHB2ENR1_SDMMC1EN; #endif -#ifdef CONFIG_STM32U5_SDMMC2EN +#ifdef CONFIG_STM32_SDMMC2 regval |= RCC_AHB2ENR1_SDMMC2EN; #endif @@ -327,7 +327,7 @@ static inline void rcc_enableahb3(void) regval |= RCC_AHB3ENR_GTZC2EN; #endif -#ifdef CONFIG_STM32U5_SRAM4 +#ifdef CONFIG_STM32_SRAM4 regval |= RCC_AHB3ENR_SRAM4EN; #endif @@ -524,7 +524,7 @@ static inline void rcc_enableapb3(void) regval |= RCC_APB3ENR_LPUART1EN; #endif -#ifdef CONFIG_STM32U5_I2C3EN +#ifdef CONFIG_STM32_I2C3 regval |= RCC_APB3ENR_I2C3EN; #endif
