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commit e68f9a7c8521aaf258acdddec641f4617690c3b4 Author: raiden00pl <[email protected]> AuthorDate: Sun Aug 16 11:13:37 2026 +0200 arch/arm/stm32l5: use common Kconfig symbols CONFIG_STM32L5_FLASHEN, OTFDEC1EN, PKAEN, SDMMC1EN, WWDGEN and GTZCEN are not defined by any Kconfig, so the RCC clock enables are dead code. Use the common CONFIG_STM32_* peripheral symbols. Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- arch/arm/src/stm32l5/hardware/stm32l5_flash.h | 4 ++-- arch/arm/src/stm32l5/stm32l562xx_rcc.c | 12 +++++----- arch/arm/src/stm32l5/stm32l5_allocateheap.c | 14 ++++++------ arch/arm/src/stm32l5/stm32l5_tim.c | 32 +++++++++++++-------------- 4 files changed, 31 insertions(+), 31 deletions(-) diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_flash.h b/arch/arm/src/stm32l5/hardware/stm32l5_flash.h index aa2363786a1..ba67ec89f81 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_flash.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_flash.h @@ -36,9 +36,9 @@ /* Flash size is known from the chip selection: * * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32L5_FLASH_CONFIG_x selects the default FLASH size based on + * CONFIG_STM32_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. This value can be overridden with - * CONFIG_STM32L5_FLASH_OVERRIDE_x + * CONFIG_STM32_FLASH_OVERRIDE_x * * Parts STM32L552xC and STM32L562xC have 256Kb of FLASH * Parts STM32L552xE and STM32L562xE have 512Kb of FLASH diff --git a/arch/arm/src/stm32l5/stm32l562xx_rcc.c b/arch/arm/src/stm32l5/stm32l562xx_rcc.c index aaac7fb7bff..38d70a41070 100644 --- a/arch/arm/src/stm32l5/stm32l562xx_rcc.c +++ b/arch/arm/src/stm32l5/stm32l562xx_rcc.c @@ -110,7 +110,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_DMAMUX1EN; #endif -#ifdef CONFIG_STM32L5_FLASHEN +#ifdef CONFIG_STM32_FLASH /* Flash memory interface clock enable */ regval |= RCC_AHB1ENR_FLASHEN; @@ -128,7 +128,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_TSCEN; #endif -#ifdef CONFIG_STM32L5_GTZCEN +#ifdef CONFIG_STM32_GTZC1 /* TSC clock enable */ regval |= RCC_AHB1ENR_GTZEN; @@ -207,19 +207,19 @@ static inline void rcc_enableahb2(void) regval |= RCC_AHB2ENR_RNGEN; #endif -#ifdef CONFIG_STM32L5_PKAEN +#ifdef CONFIG_STM32_PKA /* Public Key Accelerator clock enable */ regval |= RCC_AHB2ENR_PKAEN; #endif -#ifdef CONFIG_STM32L5_OTFDEC1EN +#ifdef CONFIG_STM32_OTFDEC1 /* On-the-fly-decryption module clock enable */ regval |= RCC_AHB2ENR_OTFDEC1EN; #endif -#ifdef CONFIG_STM32L5_SDMMC1EN +#ifdef CONFIG_STM32_SDMMC1 /* SDMMC1 clock enable */ regval |= RCC_AHB2ENR_SDMMC1EN; @@ -321,7 +321,7 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_RTCAPBEN; #endif -#ifdef CONFIG_STM32L5_WWDGEN +#ifdef CONFIG_STM32_WWDG /* Windowed Watchdog clock enable */ regval |= RCC_APB1ENR1_WWDGEN; diff --git a/arch/arm/src/stm32l5/stm32l5_allocateheap.c b/arch/arm/src/stm32l5/stm32l5_allocateheap.c index c71cae5c6c1..2be31186e6c 100644 --- a/arch/arm/src/stm32l5/stm32l5_allocateheap.c +++ b/arch/arm/src/stm32l5/stm32l5_allocateheap.c @@ -61,7 +61,7 @@ * be present in the NuttX configuration file: * * CONFIG_STM32_FSMC=y : Enables the FSMC - * CONFIG_STM32L5_FSMC_SRAM=y : Indicates that SRAM is available via the + * CONFIG_STM32_FSMC_SRAM=y : Indicates that SRAM is available via the * FSMC (as opposed to an LCD or FLASH). * CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC * address space @@ -72,7 +72,7 @@ */ #ifndef CONFIG_STM32_FSMC -# undef CONFIG_STM32L5_FSMC_SRAM +# undef CONFIG_STM32_FSMC_SRAM #endif /* STM32L5[7,8]6xx have 128 Kib in two banks, both accessible to DMA: @@ -118,13 +118,13 @@ #if CONFIG_MM_REGIONS < defined(CONFIG_STM32_SRAM2_HEAP) + \ defined(CONFIG_STM32_SRAM3_HEAP) + \ - defined(CONFIG_STM32L5_FSMC_SRAM_HEAP) + 1 + defined(CONFIG_STM32_FSMC_SRAM_HEAP) + 1 # error "You need more memory manager regions to support selected heap components" #endif #if CONFIG_MM_REGIONS > defined(CONFIG_STM32_SRAM2_HEAP) + \ defined(CONFIG_STM32_SRAM3_HEAP) + \ - defined(CONFIG_STM32L5_FSMC_SRAM_HEAP) + 1 + defined(CONFIG_STM32_FSMC_SRAM_HEAP) + 1 # warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are" #endif @@ -133,10 +133,10 @@ * configuration (as CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE). */ -#ifdef CONFIG_STM32L5_FSMC_SRAM +#ifdef CONFIG_STM32_FSMC_SRAM # if !defined(CONFIG_HEAP2_BASE) || !defined(CONFIG_HEAP2_SIZE) # error "CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE must be provided" -# undef CONFIG_STM32L5_FSMC_SRAM +# undef CONFIG_STM32_FSMC_SRAM # endif #endif @@ -352,7 +352,7 @@ void arm_addregion(void) #endif /* SRAM3 */ -#ifdef CONFIG_STM32L5_FSMC_SRAM_HEAP +#ifdef CONFIG_STM32_FSMC_SRAM_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) /* Allow user-mode access to the FSMC SRAM user heap memory */ diff --git a/arch/arm/src/stm32l5/stm32l5_tim.c b/arch/arm/src/stm32l5/stm32l5_tim.c index 0a335f83fe8..7352fc82277 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim.c +++ b/arch/arm/src/stm32l5/stm32l5_tim.c @@ -54,20 +54,20 @@ * include: * * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32L5_TIMn is defined then the CONFIG_STM32L5_TIMn_PWM may also + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may also * be defined to indicate that the timer is intended to be used for pulsed * output modulation. * - * - To control periodic ADC input sampling. If CONFIG_STM32L5_TIMn is - * defined then CONFIG_STM32L5_TIMn_ADC may also be defined to indicate + * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is + * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate * that timer "n" is intended to be used for that purpose. * - * - To control periodic DAC outputs. If CONFIG_STM32L5_TIMn is defined then - * CONFIG_STM32L5_TIMn_DAC may also be defined to indicate that timer "n" + * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_DAC may also be defined to indicate that timer "n" * is intended to be used for that purpose. * - * - To use a Quadrature Encoder. If CONFIG_STM32L5_TIMn is defined then - * CONFIG_STM32L5_TIMn_QE may also be defined to indicate that timer "n" + * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" * is intended to be used for that purpose. * * In any of these cases, the timer will not be used by this timer module. @@ -98,13 +98,13 @@ # undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32L5_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ - defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32L5_TIM6_QE) +#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) # undef CONFIG_STM32_TIM6 #endif -#if defined(CONFIG_STM32L5_TIM7_PWM) || defined (CONFIG_STM32L5_TIM7_ADC) || \ - defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32L5_TIM7_QE) +#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \ + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) # undef CONFIG_STM32_TIM7 #endif @@ -114,17 +114,17 @@ #endif #if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ - defined(CONFIG_STM32L5_TIM15_DAC) || defined(CONFIG_STM32L5_TIM15_QE) + defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) # undef CONFIG_STM32_TIM15 #endif -#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32L5_TIM16_ADC) || \ - defined(CONFIG_STM32L5_TIM16_DAC) || defined(CONFIG_STM32L5_TIM16_QE) +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \ + defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) # undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32L5_TIM17_ADC) || \ - defined(CONFIG_STM32L5_TIM17_DAC) || defined(CONFIG_STM32L5_TIM17_QE) +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \ + defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) # undef CONFIG_STM32_TIM17 #endif
