On Tue, Aug 03, 2010 at 11:22:29AM +0200, xdrudis wrote:
>
> I could try to add code similar to that above to serialICE and see
> what happens.
>
Done. It now boots serialICE once and starts the shell. I haven't downloaded
qemu, patched it and tested with a coreboot image (or the propietary bios),
but the commands I entered at the shell were answered ok as far as I
can tell.
Here's the patch against the file Rudolf Marek sent,
but I'll attach the modified file too.
--- asrock_939a785gmh.c 2010-08-03 12:08:04.000000000 +0200
+++ SerialICE/mainboard/asrock_939a785gmh.c 2010-08-03
12:02:34.000000000 +0200
@@ -42,6 +42,10 @@
static void chipset_init(void)
{
+ u32 reg32 = pci_read_config32(PCI_ADDR(0, 0x14, 0, 0x4C));
+ reg32 |= 1 << 31;
+ pci_write_config32(PCI_ADDR(0, 0x14, 0, 0x4C), reg32);
+
/* Enable LPC decoding */
pci_write_config8(PCI_ADDR(0, 0x14, 3, 0x44), (1<<6));
/*
* SerialICE
*
* Copyright (C) 2006 Uwe Hermann <[email protected]>
* Copyright (C) 2010 Rudolf Marek <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
const char boardname[33]="ALL YOUR BASE ARE BELONG TO US! ";
#define SUPERIO_CONFIG_PORT 0x2e
static void superio_init(void)
{
pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT);
/* Disable the watchdog. */
pnp_set_logical_device(SUPERIO_CONFIG_PORT, 7);
pnp_write_register(SUPERIO_CONFIG_PORT, 0x72, 0x00);
/* Enable the serial port. */
pnp_set_logical_device(SUPERIO_CONFIG_PORT, 1); /* COM1 */
pnp_set_enable(SUPERIO_CONFIG_PORT, 0);
pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8);
pnp_set_irq0(SUPERIO_CONFIG_PORT, 4);
pnp_set_enable(SUPERIO_CONFIG_PORT, 1);
pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT);
}
static void chipset_init(void)
{
u32 reg32 = pci_read_config32(PCI_ADDR(0, 0x14, 0, 0x4C));
reg32 |= 1 << 31;
pci_write_config32(PCI_ADDR(0, 0x14, 0, 0x4C), reg32);
/* Enable LPC decoding */
pci_write_config8(PCI_ADDR(0, 0x14, 3, 0x44), (1<<6));
pci_write_config8(PCI_ADDR(0, 0x14, 3, 0x48), (1 << 1) | (1 << 0));
superio_init();
}
--
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