-----Original Message-----
From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] On
Behalf Of Marc Jones
Sent: Wednesday, November 03, 2010 06:53 PM
To: Rudolf Marek
Cc: coreboot@coreboot.org
Subject: Re: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems inWin7
(revised)
]On Wed, Nov 3, 2010 at 3:34 PM, Rudolf Marek <r.ma...@assembler.cz> wrote:
]> Hi Scott,
]>
]> I tried to boot with that on famF CPU and it went well.
]> ruiktest:~#
]> ruiktest:~# lspci -vvv -s 01:05.0
]>
]> 01:05.0 VGA compatible controller: ATI Technologies Inc RS880 [Radeon HD
]> 4200] (prog-if 00 [VGA controller])
]> Subsystem: ATI Technologies Inc Device 0000
]> Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
]> Stepping- SERR- FastB2B- DisINTx-
]> Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
]> <TAbort- <MAbort- >SERR- <PERR- INTx-
]> Latency: 0, Cache Line Size: 64 bytes
]> Interrupt: pin A routed to IRQ 18
]> Region 0: Memory at e8000000 (32-bit, prefetchable) [size=128M]
]> Region 1: I/O ports at 1000 [size=256]
]> Region 2: Memory at f8100000 (32-bit, non-prefetchable) [size=64K]
]> Region 5: Memory at f8000000 (32-bit, non-prefetchable) [size=1M]
]> Expansion ROM at <unassigned> [disabled]
]> Capabilities: [50] Power Management version 3
]> Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA
]> PME(D0-,D1-,D2-,D3hot-,D3cold-)
]> Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
]> Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+
]> Address: 0000000000000000 Data: 0000
]> Kernel driver in use: radeon
]>
]> The BAR seems to be enabled. Btw I tried to boot Win7 but still got only
]> logo animation forever. Not sure what it could be.
]>
]> I agree that this patch is big improvement. We can fix the MMCONF later.
]
]Was that an ack?
]
]Maybe I misunderstand, but I don't think that there is an MMCONF
]issue. The bar disable prevents the 780 MMCONF from being moved,
]right?
]
]Just curious, have you test this with Linux?
Slax 6.12 live CD - Good. Using I/O APIC interrupts.
Linuxmint 9 live CD - Good. Using I/O APIC interrupts.
DSL linux live CD - Flood of "APIC error on CPU0: 40(40)"
I believe if SB700 ioxapic mode is not enabled everything is good.
WinXP x64 SP2 setup CD - An unexpected error (805246152) occurred at line
1831 in d:\nt\base\boot\setup\arcdisp.c
WinXP x86 SP3 setup CD - An unexpected error (805246152) occurred at line
1831 in d:\nt\base\boot\setup\arcdisp.c
Win7 x64 Ultimate setup DVD - setup completed quickly with zero problems.
All testing is with UMA graphics. I build the mahogany_fam10 project and
run it on an ECS A780GM-M3 board.
]I tried to load win7, but
]got a ACPI stop 0xA5. I suspect that my tables are not working at all.
]This is on iei kino. I will investigate more tomorrow.
The attached patch contains work in progress changes outside of the
previously RS780 patch. Apply it to the latest trunk code along with
the RS780 patch. This patch is good only for mahogany_fam10, not for
mahogany (family 0Fh). The ACPI changes need to be ported from family
10h to family 0Fh. Based on what Rudolf said recently, the family 0Fh
project method of passing TOM1 etc to ACPI is the preferred way, not
the family 10h method.
Use 1 or 2 GB of memory. Three should also work, although I am not sure
the memory init code can handle 3GB. As I recall memory above 4GB is
not yet handled correctly for booting Win7.
Hopefully you can just build a mahogany_fam10 binary and run it on Kino.
Probably any RS780 video option rom will get the job done.
Thanks,
Scott
]Marc
]
]--
]http://se-eng.com
Index: src/arch/i386/boot/coreboot_table.c
===================================================================
--- src/arch/i386/boot/coreboot_table.c (revision 6017)
+++ src/arch/i386/boot/coreboot_table.c (working copy)
@@ -488,18 +488,18 @@
return mem;
}
-static void lb_add_rsvd_range(void *gp, struct device *dev, struct resource
*res)
+static void lb_remove_rsvd_range(void *gp, struct device *dev, struct resource
*res)
{
struct lb_memory *mem = gp;
- lb_add_memory_range(mem, LB_MEM_RESERVED, res->base, res->size);
+ lb_remove_memory_range(mem, res->base, res->size);
}
-static void add_lb_reserved(struct lb_memory *mem)
+static void remove_lb_reserved(struct lb_memory *mem)
{
- /* Add reserved ranges */
+ /* Remove reserved ranges */
search_global_resources(
IORESOURCE_MEM | IORESOURCE_RESERVE, IORESOURCE_MEM |
IORESOURCE_RESERVE,
- lb_add_rsvd_range, mem);
+ lb_remove_rsvd_range, mem);
}
#if CONFIG_WRITE_HIGH_TABLES == 1
@@ -576,8 +576,8 @@
high_tables_base, high_tables_size);
#endif
- /* Add reserved regions */
- add_lb_reserved(mem);
+ /* Remove reserved regions */
+ remove_lb_reserved(mem);
#if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1)
add_mainboard_resources(mem);
Index: src/arch/i386/init/bootblock_simple.c
===================================================================
--- src/arch/i386/init/bootblock_simple.c (revision 6017)
+++ src/arch/i386/init/bootblock_simple.c (working copy)
@@ -3,6 +3,10 @@
static void main(unsigned long bist)
{
if (boot_cpu()) {
+ // workaround for simnow (simnow matches SB700 spec for 6c
+ // default, but does not match real hardware)
+ pci_io_write_config32(PCI_DEV(0, 0x14, 3), 0x6c, 0xfffffff0);
+
bootblock_northbridge_init();
bootblock_southbridge_init();
}
Index: src/cpu/amd/model_10xxx/init_cpus.c
===================================================================
--- src/cpu/amd/model_10xxx/init_cpus.c (revision 6017)
+++ src/cpu/amd/model_10xxx/init_cpus.c (working copy)
@@ -231,6 +231,7 @@
lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | F10_APSTATE_STOPPED);
}
+#if (CONFIG_ENABLE_APIC_EXT_ID == 1)
static void enable_apic_ext_id(u32 node)
{
u32 val;
@@ -239,6 +240,7 @@
val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST);
pci_write_config32(NODE_HT(node), 0x68, val);
}
+#endif
static void STOP_CAR_AND_CPU(void)
{
Index: src/cpu/amd/model_fxx/Kconfig
===================================================================
--- src/cpu/amd/model_fxx/Kconfig (revision 6017)
+++ src/cpu/amd/model_fxx/Kconfig (working copy)
@@ -4,6 +4,11 @@
select SSE
select SSE2
+config CPU_ADDR_BITS
+ int
+ default 40
+ depends on CPU_AMD_MODEL_FXX
+
config UDELAY_IO
bool
default n
Index: src/cpu/x86/mtrr/mtrr.c
===================================================================
--- src/cpu/x86/mtrr/mtrr.c (revision 6017)
+++ src/cpu/x86/mtrr/mtrr.c (working copy)
@@ -423,11 +423,8 @@
if (var_state.hole_startk || var_state.hole_sizek) {
printk(BIOS_DEBUG, "Warning: Can't set up MTRR hole for UMA due
to pre-existing MTRR hole.\n");
} else {
- // Increase the base range and set up UMA as an UC hole instead
- var_state.range_sizek += (uma_memory_size >> 10);
-
- var_state.hole_startk = (uma_memory_base >> 10);
- var_state.hole_sizek = (uma_memory_size >> 10);
+ // Reduce the dram wb mtrr range so that it does not cover the
uma at the end
+ var_state.range_sizek -= (uma_memory_size >> 10);
}
#endif
/* Write the last range */
Index: src/mainboard/amd/mahogany/Kconfig
===================================================================
--- src/mainboard/amd/mahogany/Kconfig (revision 6017)
+++ src/mainboard/amd/mahogany/Kconfig (working copy)
@@ -51,11 +51,11 @@
config MAX_CPUS
int
- default 8
+ default 2
config MAX_PHYSICAL_CPUS
int
- default 2
+ default 1
config SB_HT_CHAIN_ON_BUS0
int
@@ -81,4 +81,27 @@
hex
default 0x3060
+# ----------------overrides--------------------
+
+config VGA_BIOS
+ default y
+
+config FALLBACK_VGA_BIOS_FILE
+ default "../optionroms/vga.rom"
+
+config FALLBACK_VGA_BIOS_ID
+ default "1002,9610"
+
+config FALLBACK_PAYLOAD_FILE
+ default "../seabios-for-coreboot/out/bios.bin.elf"
+
+config DRIVERS_PS2_KEYBOARD
+ default n
+
+config VGA_ROM_RUN
+ default n
+
+config PCI_ROM_RUN
+ default n
+
endif # BOARD_AMD_MAHOGANY
Index: src/mainboard/amd/mahogany_fam10/acpi/routing.asl
===================================================================
--- src/mainboard/amd/mahogany_fam10/acpi/routing.asl (revision 6017)
+++ src/mainboard/amd/mahogany_fam10/acpi/routing.asl (working copy)
@@ -62,21 +62,16 @@
/* SB devices */
/* Bus 0, Dev 17 - SATA controller #2 */
/* Bus 0, Dev 18 - SATA controller #1 */
- Package(){0x0011FFFF, 0, INTA, 0 },
+ Package(){0x0011FFFF, 1, INTA, 0 },
- /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
- * EHCI, dev 18, 19 func 2 */
+ /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
Package(){0x0012FFFF, 0, INTA, 0 },
Package(){0x0012FFFF, 1, INTB, 0 },
- Package(){0x0012FFFF, 2, INTC, 0 },
+ Package(){0x0013FFFF, 0, INTA, 0 },
+ Package(){0x0013FFFF, 1, INTB, 0 },
+ Package(){0x0014FFFF, 2, INTA, 0 },
- Package(){0x0013FFFF, 0, INTC, 0 },
- Package(){0x0013FFFF, 1, INTD, 0 },
- Package(){0x0013FFFF, 2, INTA, 0 },
-
- /* Package(){0x0014FFFF, 1, INTA, 0 }, */
-
- /* Bus 0, Dev 20 -
F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
+ /* Bus 0, Dev 20 -
F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem
*/
Package(){0x0014FFFF, 0, INTA, 0 },
Package(){0x0014FFFF, 1, INTB, 0 },
Package(){0x0014FFFF, 2, INTC, 0 },
@@ -141,22 +136,16 @@
/* Bus 0, Dev 18 - SATA controller #1 */
Package(){0x0011FFFF, 0, 0, 22 },
- /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
- * EHCI, dev 18, 19 func 2 */
+ /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
Package(){0x0012FFFF, 0, 0, 16 },
Package(){0x0012FFFF, 1, 0, 17 },
- Package(){0x0012FFFF, 2, 0, 18 },
-
Package(){0x0013FFFF, 0, 0, 18 },
Package(){0x0013FFFF, 1, 0, 19 },
- Package(){0x0013FFFF, 2, 0, 16 },
-
- /* Package(){0x00140000, 0, 0, 16 }, */
-
+ Package(){0x0014FFFF, 0, 0, 16 },
/* Package(){0x00130004, 2, 0, 18 }, */
/* Package(){0x00130005, 3, 0, 19 }, */
- /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC;
F4:PCIBridge; F5:USB */
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC;
F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */
Package(){0x0014FFFF, 0, 0, 16 },
Package(){0x0014FFFF, 1, 0, 17 },
Package(){0x0014FFFF, 2, 0, 18 },
Index: src/mainboard/amd/mahogany_fam10/acpi_tables.c
===================================================================
--- src/mainboard/amd/mahogany_fam10/acpi_tables.c (revision 6017)
+++ src/mainboard/amd/mahogany_fam10/acpi_tables.c (working copy)
@@ -69,7 +69,13 @@
current = acpi_create_madt_lapics(current);
/* Write SB700 IOAPIC, only one */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
+ #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS *
CONFIG_MAX_PHYSICAL_CPUS < 16)
+ #define IO_APIC_ID (CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS)
+ #else
+ #define IO_APIC_ID 0
+ #endif
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ IO_APIC_ID,
IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
Index: src/mainboard/amd/mahogany_fam10/dsdt.asl
===================================================================
--- src/mainboard/amd/mahogany_fam10/dsdt.asl (revision 6017)
+++ src/mainboard/amd/mahogany_fam10/dsdt.asl (working copy)
@@ -33,13 +33,13 @@
/* FIXME the patching is not done yet! */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
- Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
- Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
- Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit
1, etc. S0 & S5 assumed */
+ Name(SSFG, 0x01) /* S1 support: bit 0, S2 Support: bit 1, etc.
S0, S4 & S5 assumed */
+ /* SB700 supports S1, S3, and S5. We lack S3
software */
+ /* support and S5 is assumed. Add S1
*/
/* USB overcurrent mapping pins. */
Name(UOM0, 0)
@@ -1168,7 +1168,7 @@
/* Note: Only need HID on Primary Bus */
Device(PCI0) {
External (TOM1)
- External (TOM2)
+ External(IOLM)
Name(_HID, EISAID("PNP0A03"))
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
Method(_BBN, 0) { /* Bus number = 0 */
@@ -1366,7 +1366,7 @@
/* Real Time Clock Device */
Device(RTC0) {
- Name(_HID, EISAID("PNP0B01")) /* AT
Real Time Clock */
+ Name(_HID, EISAID("PNP0B00")) /* AT
Real Time Clock (not PIIX4 compatible) */
Name(_CRS, ResourceTemplate() {
IRQNoFlags(){8}
IO(Decode16,0x0070, 0x0070, 0,
2)
@@ -1390,6 +1390,43 @@
})
} /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
+
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303"))
+ Name (_CID, EisaId ("PNP030B"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IO (Decode16, 0x0060,
0x0060, 0x01, 0x01)
+ IO (Decode16, 0x0064,
0x0064, 0x01, 0x01)
+ IRQNoFlags () {1}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* PS/2 mouse */
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IRQNoFlags () {12}
+ })
+ Return (TMP)
+ }
+ }
+
Device(PIC) {
Name(_HID,EISAID("PNP0000")) /* AT
Interrupt Controller */
Name(_CRS, ResourceTemplate() {
@@ -1544,90 +1581,32 @@
0xF300 /* length */
)
- Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
Memory32Fixed(READONLY, 0x000A0000, 0x00020000,
VGAM) /* VGA memory space */
Memory32Fixed(READONLY, 0x000C0000, 0x00020000,
EMM1) /* Assume C0000-E0000 empty */
Memory32Fixed(READONLY, 0x000E0000, 0x00020000,
RDBS) /* BIOS ROM area */
/* DRAM Memory from 1MB to TopMem */
- Memory32Fixed(READWRITE, 0x00100000, 0, DMLO)
/* 1MB to TopMem */
+ DWORDMemory (ResourceProducer, PosDecode,
MinFixed, MaxFixed, Cacheable, ReadWrite, 0, 0, 0, 0x00, 0,,,EMM2)
+ WORDIO (ResourceProducer, MinFixed, MaxFixed,
PosDecode, EntireRange, 0x00, 0x0D00, 0xffff, 0x00, 0xf300)
- /* BIOS space just below 4GB */
- DWORDMemory(
- ResourceProducer, PosDecode, MinFixed,
MaxFixed, Cacheable, ReadWrite,
- 0x00, /* Granularity
*/
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation
*/
- 0x00000001, /* Max-Min,
RLEN */
- ,,
- PCBM
- )
-
- /* DRAM memory from 4GB to TopMem2 */
- QWORDMemory(ResourceProducer, PosDecode,
MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, /* Granularity
*/
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation
*/
- 0x00000001, /* Max-Min,
RLEN */
- ,,
- DMHI
- )
-
- /* BIOS space just below 16EB */
- QWORDMemory(ResourceProducer, PosDecode,
MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, /* Granularity
*/
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation
*/
- 0x00000001, /* Max-Min,
RLEN */
- ,,
- PEBM
- )
-
}) /* End Name(_SB.PCI0.CRES) */
Method(_CRS, 0) {
- /* DBGO("\\_SB\\PCI0\\_CRS\n") */
-
CreateDWordField(CRES, ^EMM1._BAS, EM1B)
CreateDWordField(CRES, ^EMM1._LEN, EM1L)
- CreateDWordField(CRES, ^DMLO._BAS, DMLB)
- CreateDWordField(CRES, ^DMLO._LEN, DMLL)
- CreateDWordField(CRES, ^PCBM._MIN, PBMB)
- CreateDWordField(CRES, ^PCBM._LEN, PBML)
+
+ CreateDWordField(CRES, ^EMM2._MIN, EM2B)
+ CreateDWordField(CRES, ^EMM2._MAX, EM2E)
+ CreateDWordField(CRES, ^EMM2._LEN, EM2L)
+ Store(TOM1, EM2B)
+ Subtract(IOLM, 1, EM2E)
+ Subtract(IOLM, TOM1, EM2L)
- CreateQWordField(CRES, ^DMHI._MIN, DMHB)
- CreateQWordField(CRES, ^DMHI._LEN, DMHL)
- CreateQWordField(CRES, ^PEBM._MIN, EBMB)
- CreateQWordField(CRES, ^PEBM._LEN, EBML)
-
If(LGreater(LOMH, 0xC0000)){
Store(0xC0000, EM1B) /* Hole above
C0000 and below E0000 */
Subtract(LOMH, 0xC0000, EM1L) /*
subtract start, assumes allocation from C0000 going up */
}
- /* Set size of memory from 1MB to TopMem */
- Subtract(TOM1, 0x100000, DMLL)
-
- /*
- * If(LNotEqual(TOM2, 0x00000000)){
- * Store(0x100000000,DMHB)
DRAM from 4GB to TopMem2
- * Subtract(TOM2, 0x100000000, DMHL)
- * }
- */
-
- /* If there is no memory above 4GB, put the
BIOS just below 4GB */
- If(LEqual(TOM2, 0x00000000)){
- Store(PBAD,PBMB)
/* Reserve the "BIOS" space */
- Store(PBLN,PBML)
- }
- Else { /* Otherwise, put the BIOS just below
16EB */
- ShiftLeft(PBAD,16,EBMB) /*
Reserve the "BIOS" space */
- Store(PBLN,EBML)
- }
-
Return(CRES) /* note to change the Name buffer
*/
} /* end of Method(_SB.PCI0._CRS) */
@@ -1683,7 +1662,8 @@
/* SMBUS Support */
Mutex (SBX0, 0x00)
- OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
+ // keep base address synced with mainboard,c, SMBUS_IO_BASE
+ OperationRegion (SMB0, SystemIO, 0x6000, 0x0C)
Field (SMB0, ByteAcc, NoLock, Preserve) {
HSTS, 8, /* SMBUS status */
SSTS, 8, /* SMBUS slave status */
Index: src/mainboard/amd/mahogany_fam10/fadt.c
===================================================================
--- src/mainboard/amd/mahogany_fam10/fadt.c (revision 6017)
+++ src/mainboard/amd/mahogany_fam10/fadt.c (working copy)
@@ -39,7 +39,7 @@
#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */
#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */
#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */
-#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */
+#define ACPI_CPU_CONTROL (pm_base + 0x08) /* 6 bytes */
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
@@ -80,8 +80,8 @@
pm_iowrite(0x29, ACPI_GPE0_BLK >> 8);
/* CpuControl is in \_PR.CPU0, 6 bytes */
- pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF);
- pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8);
+ pm_iowrite(0x26, ACPI_CPU_CONTROL & 0xFF);
+ pm_iowrite(0x27, ACPI_CPU_CONTROL >> 8);
pm_iowrite(0x2A, 0); /* AcpiSmiCmdLo */
pm_iowrite(0x2B, 0); /* AcpiSmiCmdHi */
@@ -93,7 +93,7 @@
* the contents of the PM registers at
* index 20-2B to decode ACPI I/O
address.
* AcpiSmiEn & SmiCmdEn*/
- pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN
*/
+ pm_iowrite(0x10, 1<<0 | 1<<1 | 1<<3 | 1<<5 | 1<<6); /* EOSEnale [sic],
RTC_En_En, TMR_En_En, GBL_EN_EN, PciExpWakeDisEn */
outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
@@ -124,8 +124,13 @@
fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
fadt->century = 0; /* 0x7f to make rtc alrm work */
fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
- fadt->flags = 0x0001c1a5;/* 0x25; */
+ fadt->flags = 0x0001c1a5;
+ // avoid occasional checked build Assertion: ACPIEnableInitializeACPI:
Cannot write all PM1 Enable Bits
+ // Windows writes 4121h then rears 0121h, which triggers the assertion.
+ // PciExpWakeDisEn doesn't seem to do anything useful for this problem.
+ fadt->flags = 0x000181a5;
+
fadt->res2 = 0;
fadt->reset_reg.space_id = 1;
Index: src/mainboard/amd/mahogany_fam10/irq_tables.c
===================================================================
--- src/mainboard/amd/mahogany_fam10/irq_tables.c (revision 6017)
+++ src/mainboard/amd/mahogany_fam10/irq_tables.c (working copy)
@@ -1,11 +1,12 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 200x TODO <t...@todo>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -17,97 +18,48 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
#include <arch/pirq_routing.h>
-#include <cpu/amd/amdfam10_sysconf.h>
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32 + 16 * 19, /* Max. number of devices on the bus */
+ 0x00, /* Interrupt router bus */
+ (0x14 << 3) | 0x3, /* Interrupt router dev */
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0x1002, /* Vendor */
+ 0x439d, /* Device */
+ 0, /* Miniport */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0x8, /* Checksum (has to be set to some value that
+ * would give 0 after the sum of all bytes
+ * for this structure (including checksum).
+ */
+ {
+ /* bus, dev | fn, {link, bitmap}, {link, bitmap},
{link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x01, (0x05 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90},
{0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x02 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90},
{0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x03 << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90},
{0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x04 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90},
{0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x05 << 3) | 0x0, {{0x02, 0xdc90}, {0x03, 0xdc90},
{0x04, 0xdc90}, {0x01, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x06 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90},
{0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x07 << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90},
{0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x09 << 3) | 0x0, {{0x02, 0xdc90}, {0x03, 0xdc90},
{0x04, 0xdc90}, {0x01, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x0a << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90},
{0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
+ {0x02, (0x00 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90},
{0x01, 0xdc90}, {0x02, 0xdc90}}, 0xa, 0x0},
+ {0x00, (0x0b << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90},
{0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x0c << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90},
{0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x14 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90},
{0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x12 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90},
{0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x13 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90},
{0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x11 << 3) | 0x0, {{0x0c, 0xdc90}, {0x00, 0x0000},
{0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x0a, (0x00 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90},
{0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
+ {0x03, (0x05 << 3) | 0x0, {{0x0a, 0xdc90}, {0x0b, 0xdc90},
{0x0c, 0xdc90}, {0x0d, 0xdc90}}, 0xc, 0x0},
+ {0x03, (0x06 << 3) | 0x0, {{0x0b, 0xdc90}, {0x0c, 0xdc90},
{0x0d, 0xdc90}, {0x0a, 0xdc90}}, 0xd, 0x0},
+ }
+};
-
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
- u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
- u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
- u8 slot, u8 rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-extern u8 bus_isa;
-extern u8 bus_rs780[8];
-extern u8 bus_sb700[2];
-extern unsigned long sbdn_sb700;
-
unsigned long write_pirq_routing_table(unsigned long addr)
{
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- u32 slot_num;
- u8 *v;
-
- u8 sum = 0;
- int i;
-
- get_bus_conf(); /* it will find out all bus num and apic that
share with mptable.c and mptable.c and acpi_tables.c */
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be betweeen 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (u8 *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = bus_sb700[0];
- pirq->rtr_devfn = ((sbdn_sb700 + 0x14) << 3) | 4;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x1002;
- pirq->rtr_device = 0x4384;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-
- /* pci bridge */
- write_pirq_info(pirq_info, bus_sb700[0], ((sbdn_sb700 + 0x14) << 3) | 4,
- 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
- 0);
- pirq_info++;
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "write_pirq_routing_table done.\n");
-
- return (unsigned long)pirq_info;
+ return copy_pirq_routing_table(addr);
}
Index: src/mainboard/amd/mahogany_fam10/Kconfig
===================================================================
--- src/mainboard/amd/mahogany_fam10/Kconfig (revision 6017)
+++ src/mainboard/amd/mahogany_fam10/Kconfig (working copy)
@@ -13,20 +13,17 @@
select BOARD_HAS_FADT
select HAVE_BUS_CONFIG
select HAVE_OPTION_TABLE
- select GENERATE_PIRQ_TABLE
select GENERATE_MP_TABLE
select HAVE_MAINBOARD_RESOURCES
select CACHE_AS_RAM
select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
- select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
select AMDMCT
- select GENERATE_ACPI_TABLES
+ select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024
+ select TINY_BOOTBLOCK
select RAMINIT_SYSINFO
- select ENABLE_APIC_EXT_ID
- select TINY_BOOTBLOCK
select GFXUMA
config MAINBOARD_DIR
@@ -43,12 +40,16 @@
config MAX_CPUS
int
- default 8
+ default 4
config MAX_PHYSICAL_CPUS
int
- default 2
+ default 1
+config HW_MEM_HOLE_SIZE_AUTO_INC
+ bool
+ default n
+
config MEM_TRAIN_SEQ
int
default 2
@@ -67,7 +68,7 @@
config IRQ_SLOT_COUNT
int
- default 11
+ default 19
config AMD_UCODE_PATCH_FILE
string
@@ -97,4 +98,43 @@
hex
default 0
+
+# ----------------overrides--------------------
+
+config MMCONF_BASE_ADDRESS
+ default 0xf8000000
+
+config VGA_BIOS
+ default y
+
+config FALLBACK_VGA_BIOS_FILE
+ default "../optionroms/vga.rom"
+
+config FALLBACK_VGA_BIOS_ID
+ default "1002,9610"
+
+config FALLBACK_PAYLOAD_FILE
+ default "../seabios-for-coreboot/out/bios.bin.elf"
+
+config MMCONF_SUPPORT_DEFAULT
+ default y
+
+config MMCONF_SUPPORT
+ default y
+
+config MMCONF_BUS_NUMBER
+ default 16
+
+config DEFAULT_CONSOLE_LOGLEVEL
+ default 4
+
+config DRIVERS_PS2_KEYBOARD
+ default n
+
+config VGA_ROM_RUN
+ default n
+
+config PCI_ROM_RUN
+ default n
+
endif # BOARD_AMD_MAHOGANY_FAM10
Index: src/mainboard/amd/mahogany_fam10/mainboard.c
===================================================================
--- src/mainboard/amd/mahogany_fam10/mainboard.c (revision 6017)
+++ src/mainboard/amd/mahogany_fam10/mainboard.c (working copy)
@@ -154,7 +154,8 @@
int add_mainboard_resources(struct lb_memory *mem)
{
/* UMA is removed from system memory in the northbridge code, but
- * in some circumstances we want the memory mentioned as reserved.
+ * in some circumstances we want the memory mentioned as reserved
+ * in the E820 memory map.
*/
#if (CONFIG_GFXUMA == 1)
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
@@ -162,6 +163,16 @@
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
uma_memory_size);
#endif
+ // make memory claimed by flash chip memory reserved in E820 map (9 mb
for LPC)
+ lb_add_memory_range(mem, LB_MEM_RESERVED, 0xFF700000, 0x900000);
+
+ // make memory used by PCIe MMIO reserved in E820 map
+ #if defined (CONFIG_MMCONF_SUPPORT)
+ #if (CONFIG_MMCONF_SUPPORT == 1)
+ lb_add_memory_range(mem, LB_MEM_RESERVED, CONFIG_MMCONF_BASE_ADDRESS,
CONFIG_MMCONF_BUS_NUMBER * 0x100000);
+ #endif
+ #endif
+
return 0;
}
Index: src/mainboard/amd/mahogany_fam10/mptable.c
===================================================================
--- src/mainboard/amd/mahogany_fam10/mptable.c (revision 6017)
+++ src/mainboard/amd/mahogany_fam10/mptable.c (working copy)
@@ -66,7 +66,7 @@
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb700, 0x21, dword);
/* Initialize interrupt mapping */
/* aza */
Index: src/northbridge/amd/amdfam10/amdfam10_acpi.c
===================================================================
--- src/northbridge/amd/amdfam10/amdfam10_acpi.c (revision 6017)
+++ src/northbridge/amd/amdfam10/amdfam10_acpi.c (working copy)
@@ -191,6 +191,7 @@
u8 *CBBX;
u8 *CBS2;
u8 *CBB2;
+ u8 *IOLM;
int i;
@@ -210,6 +211,7 @@
CBST = ssdt+0x626;
CBB2 = ssdt+0x62d; //
CBS2 = ssdt+0x634;
+ IOLM = ssdt+0x63b;
for(i=0;i<HC_NUMS;i++) {
dword = sysconf.ht_c_conf_bus[i];
@@ -234,6 +236,12 @@
msr = rdmsr(TOP_MEM);
int_to_stream(msr.lo, TOM1);
+ dword = 0xfc000000;
+ #if (CONFIG_MMCONF_SUPPORT)
+ dword = CONFIG_MMCONF_BASE_ADDRESS;
+ #endif
+ int_to_stream(dword, IOLM);
+
int_to_stream(sysconf.sbdn, SBDN);
for(i=0;i<sysconf.hc_possible_num;i++) {
Index: src/northbridge/amd/amdfam10/amdfam10_conf.c
===================================================================
--- src/northbridge/amd/amdfam10/amdfam10_conf.c (revision 6017)
+++ src/northbridge/amd/amdfam10/amdfam10_conf.c (working copy)
@@ -827,6 +827,10 @@
#endif
/* io range allocation */
tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00);
//limit
+
+ // for now, make all mmio non-posted
+ tempreg |= 0x80;
+
for(i=0; i<nodes; i++)
pci_write_config32(__f1_dev[i], reg+4, tempreg);
tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
Index: src/northbridge/amd/amdfam10/northbridge.c
===================================================================
--- src/northbridge/amd/amdfam10/northbridge.c (revision 6017)
+++ src/northbridge/amd/amdfam10/northbridge.c (working copy)
@@ -130,7 +130,7 @@
{
u32 val;
- val = 1 | (nodeid<<4) | (linkn<<12);
+ val = 3 | (nodeid<<4) | (linkn<<12); // vga enabled and non-posted
/* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb,
0x3c0:0x3df */
f1_write_config32(0xf4, val);
Index: src/northbridge/amd/amdfam10/ssdt.asl
===================================================================
--- src/northbridge/amd/amdfam10/ssdt.asl (revision 6017)
+++ src/northbridge/amd/amdfam10/ssdt.asl (working copy)
@@ -340,6 +340,7 @@
Name (CBST, 0x88)
Name (CBB2, 0x77)
Name (CBS2, 0x66)
+ Name (IOLM, 0xcccccccc)
}
}
Index: src/northbridge/amd/amdht/h3ncmn.c
===================================================================
--- src/northbridge/amd/amdht/h3ncmn.c (revision 6017)
+++ src/northbridge/amd/amdht/h3ncmn.c (working copy)
@@ -1220,7 +1220,7 @@
STOP_HERE;
supported = HT_FREQUENCY_LIMIT_200M;
}
-
+
return (fixEarlySampleFreqCapability(supported));
}
Index: src/northbridge/amd/amdht/ht_wrapper.c
===================================================================
--- src/northbridge/amd/amdht/ht_wrapper.c (revision 6017)
+++ src/northbridge/amd/amdht/ht_wrapper.c (working copy)
@@ -119,9 +119,9 @@
*/
static BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
{
- static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE,
CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
+ static const u8 swaplist[] = {CONFIG_HT_CHAIN_UNITID_BASE,
CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF, 0, 0xFF };
/* If the BUID was adjusted in early_ht we need to do the manual
override */
- if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) &&
(CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
+ if (CONFIG_HT_CHAIN_UNITID_BASE != 0 || CONFIG_HT_CHAIN_END_UNITID_BASE
!= 0) {
printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
if ((node == 0) && (link == 0)) { /* BSP SB link */
*List = swaplist;
Index: src/southbridge/amd/sb700/sb700_early_setup.c
===================================================================
--- src/southbridge/amd/sb700/sb700_early_setup.c (revision 6017)
+++ src/southbridge/amd/sb700/sb700_early_setup.c (working copy)
@@ -305,6 +305,7 @@
{
device_t dev;
u8 byte;
+ int index;
printk(BIOS_INFO, "sb700_devices_por_init()\n");
/* SMBus Device, BDF:0-20-0 */
@@ -366,7 +367,14 @@
/* Features Enable */
pci_write_config32(dev, 0x64, 0x829E79BF); /* bit10: Enables the HPET
interrupt. */
+ //pci_write_config32(dev, 0x64, 0x829E39BF); /* bit10: Enables the HPET
interrupt. */
+ // ssd - ioxapic is on, so clear routing
+ for (index = 0; index < 16; index++) {
+ outb(index, 0xc00);
+ outb(0, 0xc01);
+ }
+
/* SerialIrq Control */
pci_write_config8(dev, 0x69, 0x90);
Index: src/southbridge/amd/sb700/sb700_sm.c
===================================================================
--- src/southbridge/amd/sb700/sb700_sm.c (revision 6017)
+++ src/southbridge/amd/sb700/sb700_sm.c (working copy)
@@ -57,12 +57,20 @@
printk(BIOS_INFO, "sm_init().\n");
ioapic_base = pci_read_config32(dev, 0x74) & (0xffffffe0); /* some
like mem resource, but does not have enable bit */
- /* Don't rename APIC ID */
- /* TODO: We should call setup_ioapic() here. But kernel hangs if cpu is
K8.
- * We need to check out why and change back. */
+
clear_ioapic(ioapic_base);
+ /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
+ #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS *
CONFIG_MAX_PHYSICAL_CPUS < 16)
+ /* Assign the ioapic ID the next available number after the processor
core local APIC IDs */
+ setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
+ #elif (CONFIG_APIC_ID_OFFSET > 0)
+ /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
+ setup_ioapic(ioapic_base, 0);
+ #else
+ #error "The processor APIC IDs must be lifted to make room for the I/O
APIC ID"
+ #endif
- /* 2.10 Interrupt Routing/Filtering */
+ /* 2.10 Interrupt Routing/Filtering */
dword = pci_read_config8(dev, 0x62);
dword |= 3;
pci_write_config8(dev, 0x62, dword);
@@ -82,10 +90,6 @@
dword |= 1 << 9;
pci_write_config32(dev, 0x78, dword); /* enable 0xCD6 0xCD7 */
- /* bit 10: MultiMediaTimerIrqEn */
- dword = pci_read_config8(dev, 0x64);
- dword |= 1 << 10;
- pci_write_config8(dev, 0x64, dword);
/* enable serial irq */
byte = pci_read_config8(dev, 0x69);
byte |= 1 << 7; /* enable serial irq function */
@@ -109,7 +113,7 @@
/* power after power fail */
on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
- get_option(&on, "power_on_after_fail");
+ get_option(&on, "power_on_after_fail");
byte = pm_ioread(0x74);
byte &= ~0x03;
if (on) {
--
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