-----Original Message----- From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] On Behalf Of Rudolf Marek Sent: Wednesday, November 03, 2010 04:34 PM To: coreboot@coreboot.org Subject: Re: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems in Win7 (revised)
]Hi Scott, ] ]I tried to boot with that on famF CPU and it went well. ]ruiktest:~# ]ruiktest:~# lspci -vvv -s 01:05.0 ] ]01:05.0 VGA compatible controller: ATI Technologies Inc RS880 [Radeon HD 4200] ](prog-if 00 [VGA controller]) ] Subsystem: ATI Technologies Inc Device 0000 ] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- ]SERR- FastB2B- DisINTx- ] Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- ]<MAbort- >SERR- <PERR- INTx- ] Latency: 0, Cache Line Size: 64 bytes ] Interrupt: pin A routed to IRQ 18 ] Region 0: Memory at e8000000 (32-bit, prefetchable) [size=128M] ] Region 1: I/O ports at 1000 [size=256] ] Region 2: Memory at f8100000 (32-bit, non-prefetchable) [size=64K] ] Region 5: Memory at f8000000 (32-bit, non-prefetchable) [size=1M] ] Expansion ROM at <unassigned> [disabled] ] Capabilities: [50] Power Management version 3 ] Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) ] Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- ] Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+ ] Address: 0000000000000000 Data: 0000 ] Kernel driver in use: radeon ] ]The BAR seems to be enabled. Btw I tried to boot Win7 but still got only logo ]animation forever. Not sure what it could be. Hello Rudolf, I was able to get the mahogany coreboot to boot Win7 on an ECS A780GM-M3 board with a family 0Fh processor installed. Here are the steps, starting with trunk: 1) Apply the revised RS780 patch (patch-rs780-2.txt). 2) Apply the Win7 changes (win7-wip-1.txt). 3) Apply the additional attached changes for family 0Fh (win7-mahogany.txt). 4) Revert file ht_wrapper.c. That quick and dirty HT3 change is not good for family 0Fh. Thanks, Scott ]I agree that this patch is big improvement. We can fix the MMCONF later. ] ]Thanks, ]Rudolf
Index: src/arch/i386/lib/ioapic.c =================================================================== --- src/arch/i386/lib/ioapic.c (revision 6024) +++ src/arch/i386/lib/ioapic.c (working copy) @@ -114,10 +114,11 @@ /* Enable Virtual Wire Mode. */ low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT; high = bsp_lapicid << (56 - 32); + + // ssd - this non-generic ioapic code causes a hang for mahogany project + //io_apic_write(ioapic_base, 0x10, low); + //io_apic_write(ioapic_base, 0x11, high); - io_apic_write(ioapic_base, 0x10, low); - io_apic_write(ioapic_base, 0x11, high); - if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) { printk(BIOS_WARNING, "IOAPIC not responding.\n"); return; Index: src/mainboard/amd/mahogany/dsdt.asl =================================================================== --- src/mainboard/amd/mahogany/dsdt.asl (revision 6024) +++ src/mainboard/amd/mahogany/dsdt.asl (working copy) @@ -33,13 +33,13 @@ /* FIXME the patching is not done yet! */ /* Memory related values */ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ Name(HPBA, 0xFED00000) /* Base address of HPET table */ - Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + Name(SSFG, 0x01) /* S1 support: bit 0, S2 Support: bit 1, etc. S0, S4 & S5 assumed */ + /* SB700 supports S1, S3, and S5. We lack S3 software */ + /* support and S5 is assumed. Add S1 */ /* USB overcurrent mapping pins. */ Name(UOM0, 0) @@ -1126,7 +1126,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External(IOLM) Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1324,7 +1324,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) @@ -1348,6 +1348,42 @@ }) } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Name (_CID, EisaId ("PNP030B")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + Device(PIC) { Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ Name(_CRS, ResourceTemplate() { @@ -1502,90 +1538,32 @@ 0xF300 /* length */ ) - Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ /* DRAM Memory from 1MB to TopMem */ - Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ + DWORDMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0, 0, 0, 0x00, 0,,, EMM2) + WORDIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x00, 0x0D00, 0xffff, 0x00, 0xf300) - /* BIOS space just below 4GB */ - DWORDMemory( - ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PCBM - ) - - /* DRAM memory from 4GB to TopMem2 */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - DMHI - ) - - /* BIOS space just below 16EB */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PEBM - ) - }) /* End Name(_SB.PCI0.CRES) */ Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ - CreateDWordField(CRES, ^EMM1._BAS, EM1B) CreateDWordField(CRES, ^EMM1._LEN, EM1L) - CreateDWordField(CRES, ^DMLO._BAS, DMLB) - CreateDWordField(CRES, ^DMLO._LEN, DMLL) - CreateDWordField(CRES, ^PCBM._MIN, PBMB) - CreateDWordField(CRES, ^PCBM._LEN, PBML) + + CreateDWordField(CRES, ^EMM2._MIN, EM2B) + CreateDWordField(CRES, ^EMM2._MAX, EM2E) + CreateDWordField(CRES, ^EMM2._LEN, EM2L) + Store(TOM1, EM2B) + Subtract(IOLM, 1, EM2E) + Subtract(IOLM, TOM1, EM2L) - CreateQWordField(CRES, ^DMHI._MIN, DMHB) - CreateQWordField(CRES, ^DMHI._LEN, DMHL) - CreateQWordField(CRES, ^PEBM._MIN, EBMB) - CreateQWordField(CRES, ^PEBM._LEN, EBML) - If(LGreater(LOMH, 0xC0000)){ Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ } - /* Set size of memory from 1MB to TopMem */ - Subtract(TOM1, 0x100000, DMLL) - - /* - * If(LNotEqual(TOM2, 0x00000000)){ - * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) - * } - */ - - /* If there is no memory above 4GB, put the BIOS just below 4GB */ - If(LEqual(TOM2, 0x00000000)){ - Store(PBAD,PBMB) /* Reserve the "BIOS" space */ - Store(PBLN,PBML) - } - Else { /* Otherwise, put the BIOS just below 16EB */ - ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ - Store(PBLN,EBML) - } - Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ @@ -1641,7 +1619,8 @@ /* SMBUS Support */ Mutex (SBX0, 0x00) - OperationRegion (SMB0, SystemIO, 0xB00, 0x0C) + // keep base address synced with mainboard.c, SMBUS_IO_BASE + OperationRegion (SMB0, SystemIO, 0x6000, 0x0C) Field (SMB0, ByteAcc, NoLock, Preserve) { HSTS, 8, /* SMBUS status */ SSTS, 8, /* SMBUS slave status */ Index: src/mainboard/amd/mahogany/mainboard.c =================================================================== --- src/mainboard/amd/mahogany/mainboard.c (revision 6024) +++ src/mainboard/amd/mahogany/mainboard.c (working copy) @@ -161,6 +161,7 @@ lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, uma_memory_size); #endif + lb_add_memory_range(mem, LB_MEM_RESERVED, 0xFF700000, 0x900000); return 0; } Index: src/mainboard/amd/mahogany/mptable.c =================================================================== --- src/mainboard/amd/mahogany/mptable.c (revision 6024) +++ src/mainboard/amd/mahogany/mptable.c (working copy) @@ -67,7 +67,7 @@ PCI_DEVFN(sbdn_sb700 + 0x14, 0)); if (dev) { dword = pci_read_config32(dev, 0x74) & 0xfffffff0; - smp_write_ioapic(mc, apicid_sb700, 0x11, dword); + smp_write_ioapic(mc, apicid_sb700, 0x21, dword); /* Initialize interrupt mapping */ /* aza */ Index: src/northbridge/amd/amdk8/amdk8_acpi.c =================================================================== --- src/northbridge/amd/amdk8/amdk8_acpi.c (revision 6024) +++ src/northbridge/amd/amdk8/amdk8_acpi.c (working copy) @@ -258,6 +258,7 @@ int lens; msr_t msr; char pscope[] = "\\_SB.PCI0"; + u32 iolm; lens = acpigen_write_scope(pscope); lens += k8acpi_write_pci_data(4, "BUSN", 0xe0); @@ -269,8 +270,11 @@ lens += acpigen_write_name_dword("SBDN", sysconf.sbdn); msr = rdmsr(TOP_MEM); lens += acpigen_write_name_dword("TOM1", msr.lo); - msr = rdmsr(TOP_MEM2); - lens += acpigen_write_name_qword("TOM2", (((uint64_t) msr.hi) << 32) | msr.lo); + iolm = 0xfc000000; + #if (CONFIG_MMCONF_SUPPORT) + iolm = CONFIG_MMCONF_BASE_ADDRESS; + #endif + lens += acpigen_write_name_dword("IOLM", iolm); lens += k8acpi_write_HT(); //minus opcode
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