Am 02.02.2011 20:11, schrieb Alex G.:
Erratum 89 is already handled on line 390:
if (!is_cpu_pre_b3()) {
/* Erratum 89 ... */
msr = rdmsr(NB_CFG_MSR);
msr.lo |= 1<< 3;
If this is also needed when CONFIG_K8_REV_F_SUPPORT == 1, then we should
move the existing one out of the
#if CONFIG_K8_REV_F_SUPPORT == 0
so it gets executed in both cases, as opposed to duplicating it.
Alex
On 02/02/2011 07:39 PM, Josef Kellermann wrote:
This patch fixes a potential system hang.
Don't know why this patch isn't included if 'CONFIG_K8_REV_F_SUPPORT == 1'.
Signed-off-by: Josef Kellermann<mailto://se...@arcor.de><se...@arcor.de>
<mailto://se...@arcor.de>
Ok,
now it gets executed in both cases.
Signed-off-by: Josef Kellermann <se...@arcor.de> <mailto://se...@arcor.de>
Index: src/cpu/amd/model_fxx/model_fxx_init.c
===================================================================
--- src/cpu/amd/model_fxx/model_fxx_init.c (Revision 6326)
+++ src/cpu/amd/model_fxx/model_fxx_init.c (Arbeitskopie)
@@ -384,24 +384,7 @@
wrmsr_amd(DC_CFG_MSR, msr);
}
- /* I can't touch this msr on early buggy cpus */
- if (!is_cpu_pre_b3()) {
- /* Erratum 89 ... */
- msr = rdmsr(NB_CFG_MSR);
- msr.lo |= 1 << 3;
-
- if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
- /* D0 later don't need it */
- /* Erratum 86 Disable data masking on C0 and
- * later processor revs.
- * FIXME this is only needed if ECC is enabled.
- */
- msr.hi |= 1 << (36 - 32);
- }
- wrmsr(NB_CFG_MSR, msr);
- }
-
/* Erratum 97 ... */
if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
msr = rdmsr_amd(DC_CFG_MSR);
@@ -445,7 +428,28 @@
msr.hi |= 1;
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
+
+#if CONFIG_K8_REV_F_SUPPORT == 0
+ /* I can't touch this msr on early buggy cpus */
+ if (!is_cpu_pre_b3())
+#endif
+ {
+ /* Erratum 89 ... */
+ msr = rdmsr(NB_CFG_MSR);
+ msr.lo |= 1 << 3;
+#if CONFIG_K8_REV_F_SUPPORT == 0
+ if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
+ /* D0 later don't need it */
+ /* Erratum 86 Disable data masking on C0 and
+ * later processor revs.
+ * FIXME this is only needed if ECC is enabled.
+ */
+ msr.hi |= 1 << (36 - 32);
+ }
+#endif
+ wrmsr(NB_CFG_MSR, msr);
+ }
/* Erratum 122 */
msr = rdmsr(HWCR_MSR);
msr.lo |= 1 << 6;
--
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