Iru had a similar problem very recently: https://www.coreboot.org/pipermail/coreboot/2017-January/082806.html
Iru - Were you able to resolve the issue you saw? On Mon, Jan 9, 2017 at 2:13 PM, ron minnich <[email protected]> wrote: > what's weird is coreboot is unchanged, just the payload. > > I am wondering if anyone recognizes this > > IMD small region: > IMD ROOT 0. bfffec00 00000400 > ROMSTAGE 1. bfffebe0 00000004 > GDT 2. bfffe9e0 00000200 > Writing AMD DCT configuration to Flash > CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) > CBFS: Locating 's3nv' > CBFS: Found @ offset 2fec0 size 10000 > Manufacturer: ef > SF: Detected W25Q128 with sector size 0x1000, total 0x1000000 > FCH SPI: Too much to write. Does your SPI chip driver use spi_crop_chunk()? > SF: Failed to send command 06: 1 > FCH SPI: Too much to write. Does your SPI chip driver use spi_crop_chunk()? > SF: Failed to send command 06: 1 > > Also ... "Too much to write" ... I'll submit a CL but, folks, "Too much to > write"? How about some numbers on this kind of message :-) > > -- > coreboot mailing list: [email protected] > https://www.coreboot.org/mailman/listinfo/coreboot -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -- coreboot mailing list: [email protected] https://www.coreboot.org/mailman/listinfo/coreboot
