Hi Mario, I have built my coreboot.rom now but still having problem booting it up (see black screen on monitor).
I am not sure few of these settings in my .config is correct or not:- CONFIG_VGA_BIOS_ID="1106,3230" (how to know and confirm this is my ID? is this important?) CONFIG_VGA_BIOS_FILE="3rdparty/blobs/mainboard/intel/apollolake_rvp/Vbt.bsf" (I have Vbt.bin and Vbt.bsf downloaded from Intel FSP_MR3, am I pionting to the correct one?) CONFIG_FMDFILE="src/mainboard/intel/leafhill/leafhill.$( CONFIG_COREBOOT_ROMSIZE_KB).fmd" (OK to use fmd from leafhill?) CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/ intel/apollolake_rvp/Vbt.bin" CONFIG_CHECKLIST_DATA_FILE_LOCATION="src/vendorcode/intel/fsp/fsp2_0/checklist" (I actually didn't see this file exist, is this important?) These settings I believed are correct, please point it out if I am wrong:- CONFIG_IFWI_FILE_NAME=(edit APLI_B0B1D0E0_IFWI_X64_R_178_10_PROD_SPI.bin using FIT.exe and change protection settings) CONFIG_IFD_BIN_PATH=(descriptor.bin decomposed from APLI_B0B1D0E0_IFWI_X64_R_178_10_PROD_SPI.bin using FIT.exe) CONFIG_FSP_M_FILE=(Fsp_M.fd split from Fsp.fd using SplitFspBin.py) CONFIG_FSP_S_FILE=(Fsp_S.fd split from Fsp.fd using SplitFspBin.py) Blow is my bootup log I can see:- coreboot-4.6-1941-g383ef6e-dirty Wed Nov 1 21:59:08 UTC 2017 bootblock starting... FMAP: Found "FLASH" version 1.1 at 300000. FMAP: base = 0 size = 1000000 #areas = 11 FMAP: area COREBOOT found @ 300800 (12179456 bytes) CBFS @ 300800 size b9d800 CBFS: 'IAFW Locator' located CBFS at [300800:e9e000) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size 7214 coreboot-4.6-1941-g383ef6e-dirty Wed Nov 1 21:59:08 UTC 2017 romstage starting... pm1_sts: 0000 pm1_en: 0000 pm1_cnt: 00000000 gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000 gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000 gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000 prsts: 00000000 tco_sts: 00000008 gen_pmcon1: 08004004 gen_pmcon2: 00003a00 gen_pmcon3: 00000000 prev_sleep_state 0 FMAP: Found "FLASH" version 1.1 at 300000. FMAP: base = 0 size = 1000000 #areas = 11 FMAP: area COREBOOT found @ 300800 (12179456 bytes) CBFS @ 300800 size b9d800 CBFS: 'IAFW Locator' located CBFS at [300800:e9e000) CBFS: Locating 'fspm.bin' CBFS: Found @ offset 18540 size 59000 FMAP: area RW_MRC_CACHE found @ eae000 (65536 bytes) *REGF fail reading first metadata block.* *MRC: region file invalid in 'RW_MRC_CACHE'* *FMAP: area RW_VAR_MRC_CACHE found @ ebe000 (4096 bytes)* *REGF fail reading first metadata block.* *MRC: region file invalid in 'RW_VAR_MRC_CACHE'* ***************************************************** looking at few lines above fail reading??!! does it matter? * CBMEM: IMD: root @ 7afff000 254 entries. IMD: root @ 7affec00 62 entries. External stage cache: IMD: root @ 7b7ff000 254 entries. IMD: root @ 7b7fec00 62 entries. CPU: frequency set to 2000 MHz WEAK: src/soc/intel/apollolake/romstage.c/mainboard_save_dimm_info called MTRR Range: Start=7a000000 End=7b000000 (Size 1000000) MTRR Range: Start=ff000000 End=0 (Size 1000000) MTRR Range: Start=7b000000 End=7b800000 (Size 800000) FMAP: area COREBOOT found @ 300800 (12179456 bytes) CBFS @ 300800 size b9d800 CBFS: 'IAFW Locator' located CBFS at [300800:e9e000) CBFS: Locating 'fallback/postcar' CBFS: Found @ offset 147680 size 421c Decompressing stage fallback/postcar @ 0x7abc6fc0 (33544 bytes) Loading module at 7abc7000 with entry 7abc7000. filesize: 0x3fd0 memsize: 0x82c8 Processing 124 relocs. Offset value of 0x78bc7000 coreboot-4.6-1941-g383ef6e-dirty Wed Nov 1 21:59:08 UTC 2017 postcar starting... FMAP: Found "FLASH" version 1.1 at 300000. FMAP: base = 0 size = 1000000 #areas = 11 FMAP: area COREBOOT found @ 300800 (12179456 bytes) CBFS @ 300800 size b9d800 CBFS: 'IAFW Locator' located CBFS at [300800:e9e000) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 7380 size 10cd8 Decompressing stage fallback/ramstage @ 0x7ab94fc0 (199152 bytes) Loading module at 7ab95000 with entry 7ab95000. filesize: 0x22678 memsize: 0x309b0 Processing 2129 relocs. Offset value of 0x7aa95000 coreboot-4.6-1941-g383ef6e-dirty Wed Nov 1 21:59:08 UTC 2017 ramstage starting... BS: BS_PRE_DEVICE times (us): entry 2 run 2 exit 0 FMAP: Found "FLASH" version 1.1 at 300000. FMAP: base = 0 size = 1000000 #areas = 11 FMAP: area COREBOOT found @ 300800 (12179456 bytes) CBFS @ 300800 size b9d800 CBFS: 'IAFW Locator' located CBFS at [300800:e9e000) CBFS: Locating 'fsps.bin' CBFS: Found @ offset 717c0 size 2a000 FMAP: area COREBOOT found @ 300800 (12179456 bytes) CBFS @ 300800 size b9d800 CBFS: 'IAFW Locator' located CBFS at [300800:e9e000) CBFS: Locating 'vbt.bin' CBFS: Found @ offset 9b800 size 1a00 I think I totally lost :( please let me know if you have any idea on how I can debug further. Thank you. -ahwan On Fri, Nov 3, 2017 at 6:18 PM, Scheithauer, Mario < [email protected]> wrote: > Hi Ahwan, > > > > Oh sorry, I forgot to attach the .config file for coreboot in my previous > mail. > > We have adjusted the memory settings (romstage.c) in the leafhill > directory for the Oxbow Hill CRB. With these settings the memory > initialization should work for Juniper Hill and Oxbow Hill CRB. Both CRBs > use the same memory modules – DDR3L. But for the Leaf Hill CRB you need > different settings, because there are other DIMM modules on it – LPDDR4. > > > > Mario > > > > > > *Von:* coreboot [mailto:[email protected]] *Im Auftrag von * > ahW@n via coreboot > *Gesendet:* Freitag, 3. November 2017 08:38 > *An:* [email protected] > *Betreff:* Re: [coreboot] Problems changing payload on Intel Leaf Hill > > > > Hi Mario, > > > > I read your reply and saw you have APL CRB Oxbow Hill with coreboot + > SeaBios running. > > I am using the same board and wanted to build the coreboot but failed. > > I think I have the required files ready (bootable UEFI BIOS file, > fitimage.bin, Fsp.fd ...) > > But still failed to build my coreboot. > > I wonder I am having correct .config settings. > > Can you share your settings? > > I check the attachment in previous list but all that is for leafhill, I > wonder are they same and valid for both Oxbox Hill and Leafhill? > > Please advise, thank you. > > > > - ahwan > > > > > > > Scheithauer, Mario Mario.Scheithauer at siemens.com > > > Wed Nov 1 16:28:45 CET 2017 > > > Previous message (by thread): [coreboot] Coreboot support on H8SGL-F > > > Next message (by thread): [coreboot] Problems changing payload on Intel > Leaf Hill > > > Messages sorted by: [ date ] [ thread ] [ subject ] [ author ] > > > Hi Tahnia, > > > > > > We have an APL CRB Oxbow Hill (B0-stepping) with coreboot (master) + > SeaBios (master) running. > > > Attached are all necessary coreboot adaptions and the config file for > SeaBios. > > > After the generation, a hack in coreboot.rom is still necessary so that > SeaBios can find the VBIOS. > > > SeaBios expects at the end of the CBFS the address from the beginning of > the CBFS section (see SeaBiosPointer.jpg). > > > Furthermore you have to pay attention to the IGD PCI ID. Intel uses > different PCI Device IDs in different CPU versions for IGD (5a84 or 5a85). > > > The console output only works via MMIO on the CRB. Therefore you need > the LPSS UART0 Micro USB port. > > > With all these adjustments we can boot a system on the CRB and have full > console output. > > > Now you just need all the necessary blobs around coreboot (IFWI, FSP, > VBIOS, uCode). > > > You can use the Intel FIT tool to separate the most of the components > from the original BIOS. > > > > > > Hope that helps, > > > Mario >
.config
Description: XML document
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