Naresh wrote…
1. Can you provide complete dump of cbfs content which is displayed at
end of make.
FMAP REGION: COREBOOT
Name Offset Type Size Comp
cbfs master header 0x0 cbfs header 32 none
fallback/romstage 0x80 stage 41108 none
cpu_microcode_blob.bin 0xa180 microcode 191488 none
fallback/ramstage 0x38e00 stage 94587 none
vgaroms/seavgabios.bin 0x4ffc0 raw 28160 none
config 0x56e40 raw 226 none
revision 0x56f80 raw 680 none
spd.bin 0x57280 spd 1536 none
fallback/dsdt.aml 0x578c0 raw 8596 none
payload_revision 0x59ac0 raw 237 none
(empty) 0x59c00 null 408 none
fspm.bin 0x59dc0 fsp 581632 none
vbt.bin 0xe7e00 raw 1168 LZMA
(4608 decompressed)
payload_config 0xe8300 raw 1760 none
(empty) 0xe8a40 null 856 none
fsps.bin 0xe8dc0 fsp 189109 LZMA
(212992 decompressed)
fallback/postcar 0x1170c0 stage 18352 none
fallback/payload 0x11b8c0 simple elf 68746 none
(empty) 0x12c5c0 null 10713048 none
bootblock 0xb63dc0 bootblock 49152 none
2. Check menuconfig or open .config in your favorite editor & check
there for file name.
I can’t see anything in the .config file that references
pci8086,9b41.rom - however see below...
3. This link might be of help:
https://www.coreboot.org/SeaBIOS#Adding_a_VGA_option_ROM
&
https://www.coreboot.org/VGA_support#How_to_retrieve_a_good_video_bios
I used the information in the “UEFI Method” section of that page to
extract the VGA BIOS that I have.
4. You need not add both vbios & vbt.
Either go with vbios or with vbt.
If you plan to use Seabios as payload then vgabios should be fine.
And let SeaBios run VGA bios to init display. Refer link above on how
to add them.
If you intend to go with vbt.bin then check if extracted vbt.bin is
correct or not by comparing it with
https://github.com/intel/FSP/blob/master/CometLakeFspBinPkg/CometLakeV/SampleCode/Vbt/Vbt.bin
I can’t guarantee that SeaBIOS will be the final payload - the end
customer hasn’t specified yet. It is likely that it will need to be
UEFI compatible so could end up being TianoCore. On that basis, I think
I need to go down the vbt.bin file route. The vbt.bin file that I have
extracted is almost identical to the one in the repo you reference.
There are some bytes that are different which I assume are the timing
specific information for the panel in this laptop.
Also you mentioned about custom board, check if PWM signal from SoC is
properly connected to eDP connector(This depends on panel),
According to the schematics, the eDP_BKLTEN and eDP_BKLTCTL signals from
the SoC go to the eDP connector (give or take the usual passives along
the way) and the eDP_VDDEN signal from the SoC is used to turn on the
3.3V supply to the LCD.
If you have Oscilloscope, then check for PWM signal. It should be high
or wave with some duty cycle. This starts only after proper display
init.
Also check VR's related to eDP backlight are able to turn on & provide
right power to LED backlight.
Will have a probe around and see if I can see what is going on.
-Andy.
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