RE: [PATCH 30/30] net/ice/base: fix Generic Checksum acronym

[Greenwalt, Paul]

Since the E830 Generic Checksum requirements have changed, this patch should 
probably wait until the code changes have been completed. GCO is no longer by 
the LAN Tx Queue Context, but will be done by the LAN Tx Context Descriptor GCS 
field. Also the RX Flex Id will be 2, not 9.

Thanks,
Paul

-----Original Message-----
From: Yang, Qiming <qiming.y...@intel.com> 
Sent: Wednesday, April 26, 2023 11:20 PM
To: dev@dpdk.org
Cc: Zhang, Qi Z <qi.z.zh...@intel.com>; Yang, Qiming <qiming.y...@intel.com>; 
sta...@dpdk.org; Greenwalt, Paul <paul.greenw...@intel.com>
Subject: [PATCH 30/30] net/ice/base: fix Generic Checksum acronym

Fixes: c31095a0b20f ("net/ice/base: add GCO defines and GCO flex descriptor")
Cc: sta...@dpdk.org

Signed-off-by: Paul Greenwalt <paul.greenw...@intel.com>
Signed-off-by: Qiming Yang <qiming.y...@intel.com>
---
 drivers/net/ice/base/ice_common.c    |  2 +-
 drivers/net/ice/base/ice_lan_tx_rx.h | 15 ++++++++-------
 2 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/drivers/net/ice/base/ice_common.c 
b/drivers/net/ice/base/ice_common.c
index 7d2a254c47..c324500b54 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -1488,7 +1488,7 @@ const struct ice_ctx_ele ice_tlan_ctx_info[] = {
        ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx,             2,      166),
        ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx,        3,      168),
        ICE_CTX_STORE(ice_tlan_ctx, int_q_state,                122,    171),
-       ICE_CTX_STORE(ice_tlan_ctx, gsc_ena,                    1,      172),
+       ICE_CTX_STORE(ice_tlan_ctx, gcs_ena,                    1,      172),
        { 0 }
 };
 
diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h 
b/drivers/net/ice/base/ice_lan_tx_rx.h
index d8ac841e46..d84f2f6db5 100644
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -747,7 +747,7 @@ enum ice_rxdid {
        ICE_RXDID_FLEX_NIC              = 2,
        ICE_RXDID_FLEX_NIC_2            = 6,
        ICE_RXDID_HW                    = 7,
-       ICE_RXDID_GSC                   = 9,
+       ICE_RXDID_GCS                   = 9,
        ICE_RXDID_COMMS_GENERIC         = 16,
        ICE_RXDID_COMMS_AUX_VLAN        = 17,
        ICE_RXDID_COMMS_AUX_IPV4        = 18,
@@ -1069,14 +1069,14 @@ enum ice_tx_desc_len_fields {  struct ice_tx_ctx_desc {
        __le32 tunneling_params;
        __le16 l2tag2;
-       __le16 gsc;
+       __le16 gcs;
        __le64 qw1;
 };
 
-#define ICE_TX_GSC_DESC_START  0  /* 7 BITS */
-#define ICE_TX_GSC_DESC_OFFSET 7  /* 4 BITS */
-#define ICE_TX_GSC_DESC_TYPE   11 /* 2 BITS */
-#define ICE_TX_GSC_DESC_ENA    13 /* 1 BIT */
+#define ICE_TX_GCS_DESC_START  0  /* 7 BITS */
+#define ICE_TX_GCS_DESC_OFFSET 7  /* 4 BITS */
+#define ICE_TX_GCS_DESC_TYPE   11 /* 2 BITS */
+#define ICE_TX_GCS_DESC_ENA    13 /* 1 BIT */
 
 #define ICE_TXD_CTX_QW1_DTYPE_S        0
 #define ICE_TXD_CTX_QW1_DTYPE_M        (0xFUL << ICE_TXD_CTX_QW1_DTYPE_S)
@@ -1188,8 +1188,9 @@ struct ice_tlan_ctx {
        u8 drop_ena;
        u8 cache_prof_idx;
        u8 pkt_shaper_prof_idx;
-       u8 gsc_ena;
+       u8 gcs_ena;
        u8 int_q_state; /* width not needed - internal - DO NOT WRITE!!! */
+       u16 tail;
 };
 
 /* LAN Tx Completion Queue data */
--
2.25.1