Before adding another SMM-related, and therefore Q35-only, dynamically detectable feature, extract the current board type check from Q35TsegMbytesInitialization() to a standalone function.
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org> Cc: Boris Ostrovsky <boris.ostrov...@oracle.com> Cc: Brijesh Singh <brijesh.si...@amd.com> Cc: Igor Mammedov <imamm...@redhat.com> Cc: Jiewen Yao <jiewen....@intel.com> Cc: Joao M Martins <joao.m.mart...@oracle.com> Cc: Jordan Justen <jordan.l.jus...@intel.com> Cc: Jun Nakajima <jun.nakaj...@intel.com> Cc: Michael Kinney <michael.d.kin...@intel.com> Cc: Paolo Bonzini <pbonz...@redhat.com> Cc: Phillip Goerl <phillip.go...@oracle.com> Cc: Yingwen Chen <yingwen.c...@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1512 Signed-off-by: Laszlo Ersek <ler...@redhat.com> --- OvmfPkg/PlatformPei/MemDetect.c | 13 +---------- OvmfPkg/PlatformPei/Platform.c | 23 ++++++++++++++++++++ 2 files changed, 24 insertions(+), 12 deletions(-) diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c index d451989f31c9..58b171fba1c8 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -53,18 +53,7 @@ Q35TsegMbytesInitialization ( UINT16 ExtendedTsegMbytes; RETURN_STATUS PcdStatus; - if (mHostBridgeDevId != INTEL_Q35_MCH_DEVICE_ID) { - DEBUG (( - DEBUG_ERROR, - "%a: no TSEG (SMRAM) on host bridge DID=0x%04x; " - "only DID=0x%04x (Q35) is supported\n", - __FUNCTION__, - mHostBridgeDevId, - INTEL_Q35_MCH_DEVICE_ID - )); - ASSERT (FALSE); - CpuDeadLoop (); - } + ASSERT (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID); // // Check if QEMU offers an extended TSEG. diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 3ba2459872d9..ca6d37cb1549 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -563,6 +563,28 @@ S3Verification ( } +VOID +Q35BoardVerification ( + VOID + ) +{ + if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { + return; + } + + DEBUG (( + DEBUG_ERROR, + "%a: no TSEG (SMRAM) on host bridge DID=0x%04x; " + "only DID=0x%04x (Q35) is supported\n", + __FUNCTION__, + mHostBridgeDevId, + INTEL_Q35_MCH_DEVICE_ID + )); + ASSERT (FALSE); + CpuDeadLoop (); +} + + /** Fetch the number of boot CPUs from QEMU and expose it to UefiCpuPkg modules. Set the mMaxCpuCount variable. @@ -646,6 +668,7 @@ InitializePlatform ( mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID); if (FeaturePcdGet (PcdSmmSmramRequire)) { + Q35BoardVerification (); Q35TsegMbytesInitialization (); } -- 2.19.1.3.g30247aa5d201 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47928): https://edk2.groups.io/g/devel/message/47928 Mute This Topic: https://groups.io/mt/34274939/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
