On 9/24/19 1:34 PM, Laszlo Ersek wrote:
> In a subsequent patch, we'll introduce new DRAM controller macros in
> "Q35MchIch9.h". Their names are too long for the currently available
> vertical whitespace, so increase the latter first.
>
> There is no functional change in this patch ("git show -b" displays
> nothing).
>
> Cc: Ard Biesheuvel <[email protected]>
> Cc: Boris Ostrovsky <[email protected]>
> Cc: Brijesh Singh <[email protected]>
> Cc: Igor Mammedov <[email protected]>
> Cc: Jiewen Yao <[email protected]>
> Cc: Joao M Martins <[email protected]>
> Cc: Jordan Justen <[email protected]>
> Cc: Jun Nakajima <[email protected]>
> Cc: Michael Kinney <[email protected]>
> Cc: Paolo Bonzini <[email protected]>
> Cc: Phillip Goerl <[email protected]>
> Cc: Yingwen Chen <[email protected]>
> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1512
> Signed-off-by: Laszlo Ersek <[email protected]>
> ---
> OvmfPkg/Include/IndustryStandard/Q35MchIch9.h | 100 ++++++++++----------
> 1 file changed, 50 insertions(+), 50 deletions(-)
>
> diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
> b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
> index 391cb4622226..614699ab38f1 100644
> --- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
> +++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
> @@ -27,56 +27,56 @@
> //
> #define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))
>
> -#define MCH_EXT_TSEG_MB 0x50
> -#define MCH_EXT_TSEG_MB_QUERY 0xFFFF
> -
> -#define MCH_GGC 0x52
> -#define MCH_GGC_IVD BIT1
> -
> -#define MCH_PCIEXBAR_LOW 0x60
> -#define MCH_PCIEXBAR_LOWMASK 0x0FFFFFFF
> -#define MCH_PCIEXBAR_BUS_FF 0
> -#define MCH_PCIEXBAR_EN BIT0
> -
> -#define MCH_PCIEXBAR_HIGH 0x64
> -#define MCH_PCIEXBAR_HIGHMASK 0xFFFFFFF0
> -
> -#define MCH_PAM0 0x90
> -#define MCH_PAM1 0x91
> -#define MCH_PAM2 0x92
> -#define MCH_PAM3 0x93
> -#define MCH_PAM4 0x94
> -#define MCH_PAM5 0x95
> -#define MCH_PAM6 0x96
> -
> -#define MCH_SMRAM 0x9D
> -#define MCH_SMRAM_D_LCK BIT4
> -#define MCH_SMRAM_G_SMRAME BIT3
> -
> -#define MCH_ESMRAMC 0x9E
> -#define MCH_ESMRAMC_H_SMRAME BIT7
> -#define MCH_ESMRAMC_E_SMERR BIT6
> -#define MCH_ESMRAMC_SM_CACHE BIT5
> -#define MCH_ESMRAMC_SM_L1 BIT4
> -#define MCH_ESMRAMC_SM_L2 BIT3
> -#define MCH_ESMRAMC_TSEG_EXT (BIT2 | BIT1)
> -#define MCH_ESMRAMC_TSEG_8MB BIT2
> -#define MCH_ESMRAMC_TSEG_2MB BIT1
> -#define MCH_ESMRAMC_TSEG_1MB 0
> -#define MCH_ESMRAMC_TSEG_MASK (BIT2 | BIT1)
> -#define MCH_ESMRAMC_T_EN BIT0
> -
> -#define MCH_GBSM 0xA4
> -#define MCH_GBSM_MB_SHIFT 20
> -
> -#define MCH_BGSM 0xA8
> -#define MCH_BGSM_MB_SHIFT 20
> -
> -#define MCH_TSEGMB 0xAC
> -#define MCH_TSEGMB_MB_SHIFT 20
> -
> -#define MCH_TOLUD 0xB0
> -#define MCH_TOLUD_MB_SHIFT 4
> +#define MCH_EXT_TSEG_MB 0x50
> +#define MCH_EXT_TSEG_MB_QUERY 0xFFFF
> +
> +#define MCH_GGC 0x52
> +#define MCH_GGC_IVD BIT1
> +
> +#define MCH_PCIEXBAR_LOW 0x60
> +#define MCH_PCIEXBAR_LOWMASK 0x0FFFFFFF
> +#define MCH_PCIEXBAR_BUS_FF 0
> +#define MCH_PCIEXBAR_EN BIT0
> +
> +#define MCH_PCIEXBAR_HIGH 0x64
> +#define MCH_PCIEXBAR_HIGHMASK 0xFFFFFFF0
> +
> +#define MCH_PAM0 0x90
> +#define MCH_PAM1 0x91
> +#define MCH_PAM2 0x92
> +#define MCH_PAM3 0x93
> +#define MCH_PAM4 0x94
> +#define MCH_PAM5 0x95
> +#define MCH_PAM6 0x96
> +
> +#define MCH_SMRAM 0x9D
> +#define MCH_SMRAM_D_LCK BIT4
> +#define MCH_SMRAM_G_SMRAME BIT3
> +
> +#define MCH_ESMRAMC 0x9E
> +#define MCH_ESMRAMC_H_SMRAME BIT7
> +#define MCH_ESMRAMC_E_SMERR BIT6
> +#define MCH_ESMRAMC_SM_CACHE BIT5
> +#define MCH_ESMRAMC_SM_L1 BIT4
> +#define MCH_ESMRAMC_SM_L2 BIT3
> +#define MCH_ESMRAMC_TSEG_EXT (BIT2 | BIT1)
> +#define MCH_ESMRAMC_TSEG_8MB BIT2
> +#define MCH_ESMRAMC_TSEG_2MB BIT1
> +#define MCH_ESMRAMC_TSEG_1MB 0
> +#define MCH_ESMRAMC_TSEG_MASK (BIT2 | BIT1)
> +#define MCH_ESMRAMC_T_EN BIT0
> +
> +#define MCH_GBSM 0xA4
> +#define MCH_GBSM_MB_SHIFT 20
> +
> +#define MCH_BGSM 0xA8
> +#define MCH_BGSM_MB_SHIFT 20
> +
> +#define MCH_TSEGMB 0xAC
> +#define MCH_TSEGMB_MB_SHIFT 20
> +
> +#define MCH_TOLUD 0xB0
> +#define MCH_TOLUD_MB_SHIFT 4
>
> //
> // B/D/F/Type: 0/0x1f/0/PCI
>
Reviewed-by: Philippe Mathieu-Daude <[email protected]>
Tested-by: Philippe Mathieu-Daude <[email protected]>
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