Yann Sionneau <[email protected]> schrieb:

>I just copy pasted Milkymist MMU documentation on github wiki : 
>https://github.com/fallen/milkymist-mmu/wiki
> From now on I will update this one with more and more informations 
>about the current MMU implementation/specifications
>
>Le 09/07/2012 12:04, Werner Almesberger a écrit :
>> Yann Sionneau wrote:
>>> *TLB size : 1024 entries
>> 1024+1024 is pretty big. I found Longsoon 2E has 16+64 [1], Itanic
>> has 96+128, PowerPC 405 has 64 (unified ?) [3], only Intel i7 comes
>> somewhat close with 576 entries per core. [4]
>Indeed it's pretty big, I think we still have a lot of unused resources
>
>in the Spartan-6 FPGA so it's not a problem if I use a lot of BlockRAM.
>Anyway the size of the TLB can be changed pretty easily in the Verilog 
>code, there is a parameter called "dtlb_sets" (or itlb_sets) which 
>contains 1024 for now.
>
>I agree we may have to do some benchmarking to chose wisely the more 
>adapted value :)
>>
>> [1]
>http://www.datasheetarchive.com/STLS2E02/Datasheet-045/DSA0019307.html
>> [2] http://www.informit.com/articles/article.aspx?p=29961&seqNum=4
>> [3] http://www.xilinx.com/ipcenter/processor_central/embedded/mmu.htm
>> [4]
>http://www.lostcircuits.com/mambo//index.php?option=com_content&task=view&id=31&Itemid=1&limit=1&limitstart=4
>>
>>> - 5'h4 : Switch to kernel mode (for debugging and developpment
>purposes only,
>>> will be removed later on)
>>> - 5'h8 : Switch to user mode (for debugging and developpment
>purposes only,
>>> will be removed later on)
>> When these are removed, how do you switch between user and kernel
>mode ?
>Upon any exception, both TLB are going into "kernel mode".
>Upon "eret" (return from exception) both TLB are going into "user
>mode".

btw what happens if the kernel is running and there is an interrupt? or if 
there are nested interrupts?

>
>I should change the name of those modes, "kernel" and "user" does not 
>reflect the real thing.
>Because Linux kernel will run in "user mode".
>I should rename those modes "physical mode" (formerly kernel mode) and 
>"virtual mode" (formerly user mode).
>




>>
>>> You select the *TLB when you write to TLBVADDR with the lowest bit
>> Hmm, seems a bit hackish. It may cost an extra instruction in the
>> DTLB fault handler.
>Yes but this simplifies the hardware: to be discussed.
>>
>>> Other bits than [21:12] and [0] of TLBPADDR and TLBVADDR are
>reserved
>>> for future use.
>> Nope, [0] is already taken for the I/D switch :-)
>I meant "Other bits than { [21:12], [0] }" and not "Other bits than 
>[21:12], and [0]".
>>
>> And another big question: what happens when a TLB fault occurs ?
>I will update the Wiki documentation to explain this :)
>>
>> - Werner
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>
>
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