Am Montag 09 Juli 2012, 00:52:24 schrieb Yann Sionneau:
> Hey,
>
> Michael Walle asked me to publish a documentation of Milkymist MMU in
> order for him to study the feasibility of implementing a model for this
> MMU in QEmu.
> Documenting is always something one needs to do at some point, so here
> it is, written very quickly in a small text file.
>
> I hope it is clear enough, if you have any question: do not hesitate to
> ask me :)
> This is not a complete documentation, it does not say anything about
> generated exceptions/TLB miss/page fault etc.
>
> Cheers !
I do have some more questions:
- are there one or two addition exception vectors? one for both ITLB and
DTLB?
- where do i read back the bad address? Looking at the source i guess i could
read it from any of the CSRs? Is there a preferred one?
- you are what is I/DTLBMA? tlb miss address?
- you're saying that it simplifies the hardware if the lowest bit selects
between DTLB and ITLB for the TLB{P|V}ADDR registers? What is the
restriction here? You're saying there are seperate registers for both TLBs.
Would it be possible to update both, the ITLB and the DTLB one, at the same
time when writing for example to TLBPADDR?
- i can't find the ITLB handling, isn't it checked in yet?
--
Michael
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