>>>>> "Yann" == Yann Sionneau <[email protected]> writes:
> Le 10/07/12 16:51, David Kuehling a écrit : >>>>>>> "Werner" == Werner Almesberger <[email protected]> writes: >> >>> Yann Sionneau wrote: >>>> *TLB size : 1024 entries >> >>> 1024+1024 is pretty big. I found Longsoon 2E has 16+64 [1], Itanic >>> has 96+128, PowerPC 405 has 64 (unified ?) [3], only Intel i7 comes >>> somewhat close with 576 entries per core. [4] >> >> Note that Loongson has 16kB pages (per default under Linux, AFAIR). >> Any reason we stick to 4kB pages? > Milkymist One board has 128 MB of DDR400 SDRAM. Which means 32768 > pages (if page size is 4 kB). I don't know the advantages of having > big pages but I guess it's better for fragmentation to have smaller > pages since it allows to have smaller slices. [..] > managing 4 kB pages for M1 costs us : 40 * 32768 = 1.24 MB > What are other advantages in using 16 kB pages ? I think RAM usage for the page tables is insignificant. Smaller pages increase the TLB miss rate (or larger pages allow you to reduce TLB size, see how Loongson only has a relatively small TLB). TLB misses look pretty expensive as they need an interrupt to be processed (i.e. much more expensive than a cache miss). Larger pages cost some RAM that is lost due to granularity of allocations, but as I said, M1 has quite a lot of RAM (when compared to, say the Nanonote). RAM loss should be proportional to the number of processes plus number of mapped shared libraries. Maybe a fully booted Linux system would lose some 100*8k RAM with 16k pages (compared to some 100*2k with 4k pages). cheers, David -- GnuPG public key: http://dvdkhlng.users.sourceforge.net/dk.gpg Fingerprint: B17A DC95 D293 657B 4205 D016 7DEF 5323 C174 7D40
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