Regarding the "streamlined synthesis flow", my primary motivation is figure
out how to add easy-to-use Migen synthesis to EDA Playground.
1. having a script that converts design.py -> design.v would be ideal, but
it doesn't exist
2. Ask the user to enter the top level Module class and the list of ports.
And then I simply run print(verilog.convert(UserModule(), ios{ports})) on
the server.
3. Tell the user to remove Simulate from the left hand pane and add the
verilog.convert command. Then look for the *.v file that was presumably
created by the user.
4. Other ideas?
-Victor
On Wed, Nov 27, 2013 at 11:18 AM, Sébastien Bourdeauducq <
[email protected]> wrote:
> On 11/27/2013 05:49 PM, Victor Lyuboslavsky wrote:
> > This would help with having a more streamlined synthesis flow.
>
> Have you tried the Migen tutorial with Mibuild?
> http://milkymist.org/3/migen-tutorial.pdf
>
> Do you see improvements for it?
>
> Sebastien
>
>
>
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