+dev list That seems to be working. Signals seem to be getting mapped to input ports. What about output ports -- does the convert method automatically figure out what is input and output? And Sink/Source variables -- are they not synthesizable?
What are a couple good example designs that I can try the verilog conversion on? On Fri, Nov 29, 2013 at 2:41 PM, Sebastien Bourdeauducq < [email protected]> wrote: > Hi, > > On 11/29/2013 09:19 PM, Victor Lyuboslavsky wrote: > > Thank you for the response. I plan to make Migen available for > > simulation on EDA Playground (using Icarus Verilog) on Sunday or Monday. > > Great! :) > > > print(verilog.convert(top, ios={name for name in dir(top) if name[0] != > > "_" and > > isinstance(getattr(top, name), Signal)})) > > ... > > > AttributeError: 'str' object has no attribute 'related' > > Yes. You need to pass a set of Signals, not a set of names, to > verilog.convert. > > So one way to do it is to use instead: > {getattr(top, name) for name in dir(top) if name[0] != "_" and > isinstance(getattr(top, name), Signal)} > > or better: > from migen.util.misc import xdir > {signal for name, signal in xdir(top, True) if name[0] != "_" and > isinstance(signal, Signal)} > > Sebastien > > >
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