On 5/27/2012 7:47 AM, Richard Elling wrote:
On May 27, 2012, at 5:11 AM, Erik Trimble wrote:
On 5/27/2012 1:22 AM, Alasdair Lumsden wrote:
SPARC has suffered the same fate as MIPS - both are nice, open
architectures, with several good freely-available designs, and
unencumbered ISAs, but their primary developer is either dead or no
longer contributing to the effort.
The problem is the CPU design is a huge black art, and it requires a
massive investment to create a new current-generation CPU. Since
the T2 design is still available, I'd be interested in seeing if
anyone would make it for embedded/appliance use. Frankly, the T2
(with some minor improvements) makes a really, really nice:
NFS server
Static web appliance
SAN head
load balancer/firewall
The cost model doesn't work out. In the IC business, the cost of a
chip is a function of:
cost = packaging (fixed) cost + die size cost (cost/die and yield)
Consider two different approaches:
1. make the biggest die you can package (about 450 mm sq) and put as
much cool tech
on the die to be compelling, but limited to current node - 1 due
to lack of IC fab ownership
2. figure out what price you want people to pay, build a processor
that fits the corresponding
die size and packaging constraint, and use the latest node because
you own the fab
As you can guess, #1 is Sun and #2 is Intel. The result is that
manufacturing an Intel processor
tends to stay at the same cost over time (perhaps $25 - $150,
depending on market+family), and
allows Intel to gain cost advantage as they rev fab technology (a very
effective strategy).
Meanwhile, the minimum cost for a T2 processor is in the $2-4k range.
So the answer is: zero change the T2 ever going to be feasible for
embedded or appliance use,
its cost model doesn't fit the embedded market. Processors with
smaller die size and less power
dominate the embedded/appliance space, eg ARM today.
-- richard
I don't have hard numbers, but my last impression while at Snoracle was
that the T1/T2 were being made on 90nm - that is, at *least* two full
generations behind what AMD & Intel were doing at the time (45nm). Even
after the shrink to 65nm it's a full 3 gen behind the latest 22nm.
Because it was quite behind the current bleeding edge in terms of
process size, that meant there were a large number of available contract
Fabs that were able to manufacture the chip, and per-chip costs were
significantly less than one might expect for "current era" CPU. That
is, sure, Intel can do 22nm nowadays, but the plant that makes that
costs $20 BILLLION or more. That's a whole lot of sunk cost to recuperate.
The T2's advantage in this market is that someone else has already
footed the sunken cost of the Fab, and that it's really not competing
for Fab time with any other CPU except some ARMs or random weird stuff.
That means, the $/mm2 of space for them is dirt cheap compared to the
equivalent Intel/AMD chip. Not to mention the fact that a T2 has less
than half the number of transistors that a Xeon 76xx has. Sure, a Xeon
7600 takes up half the die space that a T2 does, but the per/mm2 costs
of 32nm are HUGE compared to a contract-house 90nm one.
Given what we paid for full systems and upgrades in-house at Sun, a T2
CPU couldn't have cost more than a couple hundred dollars to make.
Certainly not in the $2-4k range.
ARM chips certainly aren't doing well in the appliance/embedded market
for traditional "sealed computer disguised as something else" except at
the extreme low-end consumer field. Portable devices, sure. But even
the MIPS and Freescale stuff are killing it at the embedded controller
market (ATMs, Elevator Controllers, Car computers, etc.). The T2 and
related designs certainly aren't going to storm the world, but there's a
relatively big niche where they *could* be fairly dominant. We'll have
to see.
For comparison:
Westmere-EP (Xeon 5600-series): 32nm process, 240 mm2 die size, 1.2
Billion transistors
T2: 65nm process, 342mm2 die size, 500 million transistors
So, a T2 is about 45% bigger than a X5600 (i.e. about two-thirds the
yield per wafer). I'm going to hazard a guess that it costs almost an
order of magnitude less to make a wafer at 65nm than it does at 32nm.
-Erik
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