Hi Rob, On 11/18/2015 6:48 PM, Rob Herring wrote: > +dt list > > On Wed, Nov 18, 2015 at 4:55 AM, Archit Taneja <architt at codeaurora.org> > wrote: >> Add additional property info needed for DSIv2 DT. > > Please use get_maintainers.pl.
Sorry about that, missed out doing that posting this time. > >> Signed-off-by: Archit Taneja <architt at codeaurora.org> >> --- >> Documentation/devicetree/bindings/display/msm/dsi.txt | 10 +++++++++- >> 1 file changed, 9 insertions(+), 1 deletion(-) >> >> diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt >> b/Documentation/devicetree/bindings/display/msm/dsi.txt >> index f344b9e..ca65a34 100644 >> --- a/Documentation/devicetree/bindings/display/msm/dsi.txt >> +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt >> @@ -13,18 +13,25 @@ Required properties: >> - power-domains: Should be <&mmcc MDSS_GDSC>. >> - clocks: device clocks >> See Documentation/devicetree/bindings/clocks/clock-bindings.txt for >> details. >> -- clock-names: the following clocks are required: >> +- clock-names: these vary based on the DSI version. For DSI6G: >> * "bus_clk" >> * "byte_clk" >> + * "byte_clk_src > > This sounds like the parent of byte_clk. Is that really a clock within > the block? byte_clk_src isn't in the block, but byte_clk_src's parent is one of the PLLs in this block. We take this clock so that we can re-parent it to an appropriate PLL. The decision of what PLL to choose needs to be done by the DSI block's driver. > >> * "core_clk" >> * "core_mmss_clk" >> * "iface_clk" >> * "mdp_core_clk" >> * "pixel_clk" >> + * "pixel_clk_src" >> + For DSIv2, we need a few more: > > What is the overall order of clocks? As listed? Order in which the driver does clk_get? It uses the clock name to get each one individually, so the order doesn't matter as such. I don't think it the order of clk_get in the driver is the same as what's been listed here. I can fix it if that's the norm. Thanks, Archit > >> + * "dsi_clk_src" >> + * "esc_clk_src" >> + * "src_clk" >> - vdd-supply: phandle to vdd regulator device node >> - vddio-supply: phandle to vdd-io regulator device node >> - vdda-supply: phandle to vdda regulator device node >> - qcom,dsi-phy: phandle to DSI PHY device node >> +- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2) >> >> Optional properties: >> - panel at 0: Node of panel connected to this DSI controller. >> @@ -51,6 +58,7 @@ Required properties: >> * "qcom,dsi-phy-28nm-hpm" >> * "qcom,dsi-phy-28nm-lp" >> * "qcom,dsi-phy-20nm" >> + * "qcom,dsi-phy-28nm-8960" >> - reg: Physical base address and length of the registers of PLL, PHY and >> PHY >> regulator >> - reg-names: The names of register regions. The following regions are >> required: >> -- >> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, >> hosted by The Linux Foundation >> >> _______________________________________________ >> dri-devel mailing list >> dri-devel at lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/dri-devel -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project