On 11/21/2015 1:29 AM, Rob Herring wrote:
> +Stephen
>
> On Wed, Nov 18, 2015 at 9:24 AM, Archit Taneja <architt at codeaurora.org> 
> wrote:
>> Hi Rob,
>>
>> On 11/18/2015 6:48 PM, Rob Herring wrote:
>>>
>>> +dt list
>>>
>>> On Wed, Nov 18, 2015 at 4:55 AM, Archit Taneja <architt at codeaurora.org>
>>> wrote:
>>>>
>>>> Add additional property info needed for DSIv2 DT.
>>>
>>>
>>> Please use get_maintainers.pl.
>>
>>
>> Sorry about that, missed out doing that posting this time.
>>
>>>
>>>> Signed-off-by: Archit Taneja <architt at codeaurora.org>
>>>> ---
>>>>    Documentation/devicetree/bindings/display/msm/dsi.txt | 10 +++++++++-
>>>>    1 file changed, 9 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt
>>>> b/Documentation/devicetree/bindings/display/msm/dsi.txt
>>>> index f344b9e..ca65a34 100644
>>>> --- a/Documentation/devicetree/bindings/display/msm/dsi.txt
>>>> +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt
>>>> @@ -13,18 +13,25 @@ Required properties:
>>>>    - power-domains: Should be <&mmcc MDSS_GDSC>.
>>>>    - clocks: device clocks
>>>>      See Documentation/devicetree/bindings/clocks/clock-bindings.txt for
>>>> details.
>>>> -- clock-names: the following clocks are required:
>>>> +- clock-names: these vary based on the DSI version. For DSI6G:
>>>>      * "bus_clk"
>>>>      * "byte_clk"
>>>> +  * "byte_clk_src
>>>
>>>
>>> This sounds like the parent of byte_clk. Is that really a clock within
>>> the block?
>>
>>
>> byte_clk_src isn't in the block, but byte_clk_src's parent is one of
>> the PLLs in this block. We take this clock so that we can re-parent
>> it to an appropriate PLL. The decision of what PLL to choose needs to
>> be done by the DSI block's driver.
>
> Seems like abuse to me. The list of clocks should match what are
> inputs to the block, not what the driver happens to need. Without a
> full understanding of the clock tree here, I don't have a suggestion.
> Maybe Stephen does.

We don't need specify byte_clk_src (and other xyz_clk_src clocks) via
DT. There is a static link set up between byte_clk and byte_clk_src by
our clock driver that never changes. We can retrieve it in the driver
itself using clk_get_parent(byte_clk). This way we stick to only
input clocks.

Stephen, does that sound okay?

>
>>>>      * "core_clk"
>>>>      * "core_mmss_clk"
>>>>      * "iface_clk"
>>>>      * "mdp_core_clk"
>>>>      * "pixel_clk"
>>>> +  * "pixel_clk_src"
>>>> +  For DSIv2, we need a few more:
>>>
>>>
>>> What is the overall order of clocks? As listed?
>>
>>
>> Order in which the driver does clk_get? It uses the clock
>> name to get each one individually, so the order doesn't matter
>> as such.
>
> The order in DT. You may use the names, but the order should still be 
> specified.

Okay. I'll cross check and make sure the order is as in our DT files.

Archit

>
> Rob
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